vpx3224d ETC-unknow, vpx3224d Datasheet
vpx3224d
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vpx3224d Summary of contents
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MICRONAS Edition Nov. 9, 1998 6251-432-2PD PRELIMINARY DATA SHEET VPX 3225D, VPX 3224D Video Pixel Decoders MICRONAS ...
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VPX 3225D, VPX 3224D Contents Page Section Title 6 1. Introduction 7 1.1. System Architecture 8 2. Functional Description 8 2.1. Analog Front-End 8 2.1.1. Input Selector 8 2.1.2. Clamping 8 2.1.3. Automatic Gain Control 8 2.1.4. Analog-to-Digital Converters 8 ...
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PRELIMINARY DATA SHEET Contents, continued Page Section Title 26 2.9. Operational Modes 26 2.9.1. Open Mode 26 2.9.2. Scan Mode 28 2.10. Windowing the Video Field 29 2.11. Temporal Decimation 30 2.12. Data Slicer 30 2.12.1. Slicer Features 30 2.12.2. ...
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VPX 3225D, VPX 3224D Contents, continued Page Section Title 45 3. Specifications 45 3.1. Outline Dimensions 48 3.2. Pin Connections and Short Descriptions 45 3.3. Pin Descriptions 47 3.4. Pin Configuration 48 3.5. Pin Circuits 50 4. Electrical Characteristics 50 ...
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PRELIMINARY DATA SHEET Contents, continued Page Section Title 83 7. Application Notes 83 7.1. Differences between VPX 3220A and VPX 322xD 83 7.2. Impact to Signal to Noise Ratio 83 7.3. Control Interface 83 7.3.1. Symbols 83 7.3.2. Write Data ...
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VPX 3225D, VPX 3224D Video Pixel Decoder Release Note: This data sheet describes functions and characteristics of VPX 322xD–C3 and D4. Revi- sion bars indicate significant changes to the pre- vious edition. 1. Introduction The Video Pixel Decoders VPX 3225D ...
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PRELIMINARY DATA SHEET 1.1. System Architecture The block diagram (Fig. 1–1) illustrates the signal flow through the VPX. A sampling stage performs 8-bit A/D conversion, clamping, and AGC. The color decoder sep- arates the luma and chroma signals, demodulates the ...
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VPX 3225D, VPX 3224D 2. Functional Description The following sections provide an overview of the differ- ent functional blocks within the VPX. Most of them are controlled by the Fast Processor (‘FP’) embedded in the decoder. For controlling, there are ...
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PRELIMINARY DATA SHEET Table 2–1: ADC input range for PAL input signal and corresponding output signal ranges Signal CVBS 100% CVBS 75% CVBS video (luma) sync height clamp level Chroma burst 100% Chroma 75% Chroma bias level CVBS/Y upper headroom ...
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VPX 3225D, VPX 3224D 2.2. Color Decoder In this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. A block diagram ...
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PRELIMINARY DATA SHEET 2.2.3. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter, all luma information ...
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VPX 3225D, VPX 3224D In the NTSC compensated mode, Fig. 2–7 c), the color signal is averaged for two adjacent lines. Thus, cross- color distortion and chroma noise is reduced. In the NTSC combfilter mode, Fig. 2–7 d), the delay ...
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PRELIMINARY DATA SHEET 2.3. Video Sync Processing Fig. 2–10 shows a block diagram of the front-end sync processing. To extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 ...
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VPX 3225D, VPX 3224D 2.5. Component Processing Recovery of the YCbCr components by the decoder is followed by horizontal resizing and skew compensation. Contrast enhancement with noise shaping can also be applied to the luminance signal. Vertical resizing is sup- ...
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PRELIMINARY DATA SHEET 2.5.1. Horizontal Resizer The operating range of the horizontal resizer was cho- sen to serve the widest possible range of applications and source formats (number of lines, aspect ratio, etc...). Table 2–2 lists several examples for video ...
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VPX 3225D, VPX 3224D 2.5.2. Skew Correction The VPX delivers orthogonal pixels with a fixed clock even in the case of non-broadcast signals with substan- tial horizontal jitter (VCRs, laser disks, certain portions of the 6 o’clock news...). This is ...
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PRELIMINARY DATA SHEET 2.6. Video Output Interface Contrary to the component processing stage running at a clock rate of 20.25 MHz, the output formatting stage (Fig. 2–16) receives the video samples at a pixel trans- port rate of 13.5 MHz. ...
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VPX 3225D, VPX 3224D 2.6.1.2. Embedded Reference Headers/ITU-R656 The VPX supports an output format which is designed to be compliant with the ITU-R656 recommendation activated by setting Bit[1:0] of FP-RAM 0x150 to 01. The 16-bit video data must ...
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PRELIMINARY DATA SHEET be checked and corrected if necessary to assure an ap- propriate size of VACT for both data and ancillary header. Table 2–5 shows the coding of the ancillary header in- formation. The word I[2:0] contains a value ...
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VPX 3225D, VPX 3224D 2.6.1.3. Embedded Timing Codes (BStream) In this mode, several event words are inserted into the pixel stream for timing information activated by set- ting Bit[1:0] of FP-RAM 0x150 to 10. Each event word consists ...
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PRELIMINARY DATA SHEET Table 2–7: Luminance control codes Luma Value Video Event 01 VACT end 02 VACT begin 03 HREF active line 04 HREF blank line 05 VREF even 06 VREF odd DATA FFh 03h FFh (Port A) VACT HREF ...
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VPX 3225D, VPX 3224D 2.7.2. Half Clock Mode For applications demanding a low bandwidth for the transmission between video decoder and graphics con- troller, the clock signal qualifying the output pixels (PIXCLK) can be divided by 2. This mode is ...
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PRELIMINARY DATA SHEET 2.8. Video Reference Signals The complete video interface of the VPX runs at a clock rate of 13.5 MHz. It mainly generates two reference sig- nals for the video timing: a horizontal reference (HREF) and a vertical ...
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VPX 3225D, VPX 3224D 625 Input CVBS (50 Hz), PAL 3 Input CVBS (60 Hz), NTSC HREF VREF FIELD Fig. 2–27: VREF timing for ODD fields 312 313 Input CVBS (50 Hz), PAL 265 266 Input CVBS (60 Hz), NTSC ...
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PRELIMINARY DATA SHEET 2.8.4. VACT The ‘video active’ signal is a qualifier for valid video sam- ples. Since scaled video data is stored internally, there are no invalid pixel within the VACT interval. VACT has a defined position relative to ...
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VPX 3225D, VPX 3224D 2.9. Operational Modes The relationship between the video timing signals (HREF and VREF) and the analog input video is deter- mined by the selected operational mode. Three such modes are available: the Open Mode, the Forced ...
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PRELIMINARY DATA SHEET Table 2–10: Transition behavior as a function of operating mode Transition Behavior as a Function of Operating Mode Transition Mode Power up/Reset Open (no video) no video video Open Scan video no video Open Scan video video ...
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VPX 3225D, VPX 3224D 2.10. Windowing the Video Field For each input video field, two non-overlapping video windows can be defined. The dimensions of these win- 2 dows are supplied via I C commands. The presence of two windows allows ...
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PRELIMINARY DATA SHEET 4 4 267 5 5 268 6 6 269 7 7 270 281 19 19 282 20 20 283 21 21 284 260 260 523 261 261 524 262 ...
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VPX 3225D, VPX 3224D 2.12. Data Slicer The data slicer is only available on VPX 3225D. Soft- 2 ware drivers accessing the slicer I therefore check the VPX part number. 2.12.1. Slicer Features – 8-bit digital FBAS input – 8-bit ...
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PRELIMINARY DATA SHEET 2.12.3. Slicer Functions The data slicer is inserted between the video ADC and the video output interface (see Fig. 1–1). It operates completely independent of the video front-end proces- sing and has its own sync separator and ...
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VPX 3225D, VPX 3224D The number of useful data bytes at the output is pro- grammable and should be set accordingly to the se- lected teletext standard. To get “n” data bytes, the value “n+1” has to be programmed, because ...
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PRELIMINARY DATA SHEET 2.13. VBI Data Acquisition The VPX supports two different data acquisition modes for the vertical blanking interval: a bypass mode for raw data of the vertical blanking interval and a data slicer mode in which dedicated hardware ...
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VPX 3225D, VPX 3224D 2.13.2. Sliced VBI Data The sliced data mode is enabled with bit[1] of the FP-RAM 0x138 (vbimode). This mode uses the inte- grated data slicer (available only on VPX 3225D) and delivers decoded data samples to ...
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PRELIMINARY DATA SHEET 2.14. Control Interface 2.14.1. Overview Communication between the VPX and the external con- 2 troller is performed serially via the I C bus (pins SCL and SDA). There are basically two classes of registers in the VPX. ...
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VPX 3225D, VPX 3224D Write to Hardware Control Registers Read from Hardware Control Registers ACK 2 Note C-Bus Start ...
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PRELIMINARY DATA SHEET 2.15. Initialization of the VPX 2.15.1. Power-on-Reset In order to completely specify the operational mode of the VPX, appropriate values must be loaded into the I and FP registers. After powering the VPX, an internal 2 power-on-reset ...
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VPX 3225D, VPX 3224D 2.16. JTAG Boundary-Scan, Test Access Port (TAP) The design of the Test Access Port, which is used for Boundary-Scan Test, conforms to standard IEEE 1149.1-1990, with one exception. Also included is a list of the mandatory ...
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PRELIMINARY DATA SHEET Tristate Cell Each group of output signals, which are tristatable, is controlled by a boundary scan cell (output cell type). This allows either the normal system signal or the scanned signal to control the tristate control. In ...
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VPX 3225D, VPX 3224D 2.16.4.3. Self-Test Operation (Section 12.3.1.b.iii of IEEE 1149.1-1990). There is no self-test operation included in the VPX de- sign which is accessible via the TAP. 2.16.4.4. Test Data Registers (Section 12.3.1.b.iv of IEEE 1149.1-1990). The VPX ...
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PRELIMINARY DATA SHEET $F Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê 1 Test-Logic-Reset Ê Ê Ê Ê Ê Ê Run / Idle State Code TDO inactive Í Í Í Í Í ...
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VPX 3225D, VPX 3224D ––************************************************************* –– –– This is the BSDL for the 44-Pin Version of the VPXD design. –– ––************************************************************* Library IEEE; Use work.STD_1149_1_1990.ALL; Entity VPXD_44 is Generic (Physical_Pin_Map:string := ”UNDEFINED”); Port( TDI,TCK,TMS: in bit; TDO,HREF,VREF,FIELD: out bit; A: ...
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PRELIMINARY DATA SHEET ”SAMPLE (001),” & ”IDCODE (010),” & ”MASTERMODE (011),” & ”HIGHZ (100),” & ”CLAMP” (110),” & ”BYPASS (100,101,110,111),”; Attribute Register_Access of VPXD_44: entity is ”BOUNDARY (EXTEST,SAMPLE),” & ”BYPASS (BYPASS, HIGHZ, CLAMP),” & ”IDCODE[32] (IDCODE),” & ”MASTERMODE[8] (MASTERMODE) ”; ...
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VPX 3225D, VPX 3224D 2.17. Enable/Disable of Output Signals In order to enable the output pins of the VPX to achieve the high impedance/tristate mode, various controls have been implemented. The following paragraphs give an overview of the different tristate ...
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PRELIMINARY DATA SHEET 3. Specification 3.1. Outline Dimensions 1 1 17.525 0.125 Fig. 3–1: 44-Pin Plastic Leaded Chip Carrier Package (PLCC44) Weight approximately 2.5 g Dimensions ...
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VPX 3225D, VPX 3224D Pin Connections and Short Descriptions, continued Pin No. Pin Name Type PLCC44 15 A2 OUT 16 A1 OUT 17 A0 OUT LLC OUT 20 VACT OUT 21 B7 OUT 22 B6 OUT ...
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PRELIMINARY DATA SHEET 3.3. Pin Descriptions Pins 44, 1 – JTAG Input Pins, TMS, TDI (Fig. 3–4) Test Mode Select and Test Data Input signals of the JTAG Test Access Port (TAP). Both signals are inputs with a TTL compatible ...
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VPX 3225D, VPX 3224D 3.4. Pin Configuration TDO (LLC2, DACT PVDD PIXCLK PVSS Fig. 3–2: 44-pin PLCC package. 3.5. Pin Circuits VDD Pin VSS Fig. 3–3: TCK, OE, RES PVDD VDD Pin ...
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PRELIMINARY DATA SHEET VDD VSS RES PVDD P FIELD Pin N PVSS Fig. 3–7: Reference Signal FIELD and wake-up selection LOWPOW on positve edge of RES XTAL2 P 0.5M XTAL1 N Fig. 3–8: Crystal Oscillator AVDD – P BIAS + ...
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VPX 3225D, VPX 3224D 4. Electrical Characteristics 4.1. Absolute Maximum Ratings Symbol Parameter T Ambient Temperature A T Storage Temperature S T Junction Temperature J V Supply Voltage, all Supply Inputs SUB P Power Dissipation due to package TOT MAX ...
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PRELIMINARY DATA SHEET 4.2. Recommended Operating Conditions Symbol Parameter T Ambient Operating Temperature A V Analog Supply Voltage SUPA V Digital Supply Voltage SUPD V Pad Supply Voltage SUPP f Clock Frequency XTAL 1) could also be connected to the ...
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VPX 3225D, VPX 3224D 2 4.2.2. Recommended I C Conditions (Timing diagram see Fig. 5–3 on page 61) Symbol Parameter C-BUS Input Low Voltage IMIL C-BUS Input High Voltage IMIH C-BUS ...
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PRELIMINARY DATA SHEET 4.2.4. Recommended Crystal Characteristics Symbol Parameter T Operating Ambient Temperature A f Parallel Resonance Frequency P with Load Capacitance Accuracy of Adjustment Frequency Temperature Drift Series Resistance ...
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VPX 3225D, VPX 3224D 4.3. Characteristics 4. SUPD SUPD/A SUPP 4.3.1. Current Consumption Symbol Parameter ...
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PRELIMINARY DATA SHEET 4.3.4. Characteristics, Analog Front-End and ADCs Symbol Parameter V Reference Voltage Top VRT Luma – Path R Input Resistance VIN C Input Capacitance VIN V Full Scale Input Voltage VIN V Full Scale Input Voltage VIN AGC ...
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VPX 3225D, VPX 3224D 4.3.5. Characteristics, Control Bus Interface (Timing diagram see Fig. 5–3 on page 61) Symbol Parameter V Output Low Voltage IMOL C-Data Output Hold Time after IMOL1 Falling Edge of Clock SCL 2 t ...
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PRELIMINARY DATA SHEET 4.3.7. Characteristics, Digital Inputs/Outputs Symbol Parameter Digital Input Pins TMS, TDI, TCK, RES, OE, SCL, SDA C Input Capacitance IN I Input Leakage Current I Input Pins TCK, RES, OE, SCL, SDA I Input Leakage Current I ...
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VPX 3225D, VPX 3224D 4.3.9. Digital Video Interface Symbol Parameter Data and Control Pins (LLC to A[7:0], B[7:0], HREF, VREF, FIELD, VACT: The following timing specifications refer to the timing diagrams of section 5.7. on page 64. t Output Hold ...
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PRELIMINARY DATA SHEET 4.3.10.1. TTL Output Driver Description The driving capability/strength is controlled by the state 2 of the two I C registers F8 and F9 hex A special PVDD, PVSS supply is used only to support the digital output ...
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VPX 3225D, VPX 3224D 5. Timing Diagrams 5.1. Power-Up Sequence The reset should not reach high level before the oscillator has started. This requires a reset delay of >1 ms (see Fig.5–1). Supplies Crystal Oscillator RES Fig. 5–1: Power-up sequence ...
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PRELIMINARY DATA SHEET 5.3. Control Bus Timing Diagram (Data: MSB first) SCL T I2C1 SDA as input SDA as output 2 Fig. 5– bus timing diagram Micronas VPX 3225D, VPX 3224D I2C4 I2C3 T ...
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VPX 3225D, VPX 3224D 5.4. Output Enable by Pin OE OE Signals A[7:0], B[7:0] Synchronizing the OE signal with clock LLC: 2 controlled register ’OENA’ h’f2 bit[5] oeqdel = latoeq = 0 Signals A[7:0], ...
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PRELIMINARY DATA SHEET 5.5. Timing of the Test Access Port TAP TCK TDI, TMS TDO Fig. 5–5: Timing of Test Access Port TAP 5.6. Timing of all Pins connected to the Boundary-Scan-Register-Chain TCK Inputs Outputs Fig. 5–6: Timing with respect ...
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VPX 3225D, VPX 3224D 5.7. Timing Diagram of the Digital Video Interface Clock Output LLC A[7:0], B[7:0] HREF, VREF, FIELD, VACT Fig. 5–7: Video output interface (detailed timing) 5.7.1. Characteristics, Clock Signals LLC LLC2 PIXCLK Fig. 5–8: Clocks: LLC, LLC2, ...
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PRELIMINARY DATA SHEET 6. Control and Status Registers The following tables give definitions for the VPX control and status registers. The number of bits indicated for each register in the table is the number of bits imple- mented in the ...
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VPX 3225D, VPX 3224D Address Number Mode Hex of Bits h’12 12 r/w h’ h’ h’ h’ h’ h’ h’ h’ h’ ...
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PRELIMINARY DATA SHEET Address Number Mode Hex of Bits h’132 12 w h’134 12 w h’135 12 w h’136 12 w h’137 12 w h’138 12 w h’139 12 w h’140 h’141 12 r h’150 12 w ...
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VPX 3225D, VPX 3224D 2 6.1.1. Description Control and Status Registers 2 Table 6–1: I C-Registers VPX Front-End Address Number Mode Hex of bits h’ h’ h’ h’38 16 w/r 2 ...
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PRELIMINARY DATA SHEET Address Number Mode Hex of bits h’ h’ h’ direct direct direct direct direct direct direct direct h’ Micronas VPX 3225D, VPX 3224D 2 I C-Registers VPX Back-End Function ...
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VPX 3225D, VPX 3224D 2 Table 6–3: I C-Registers VPX Slicer Address Number Mode Function Hex of bits h’ sync slicer bit [6:0] : bit [7] : h’ sync status bit [5:0] : bit [6] : ...
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PRELIMINARY DATA SHEET Address Number Mode Function Hex of bits h’ accumulator mode bit [0] : bit [1] : bit [2] : bit [3] : bit [4] : bit [5] : bit [7:6] : h’ read ...
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VPX 3225D, VPX 3224D 6.1.2. Description of FP Control and Status Registers Table 6–4: FP-RAM VPX Front-End Address Number Mode Function Hex of Bits h’ Standard select: bit [2:0] bit [3] bit [5:4] bit [6] Option bits allow ...
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PRELIMINARY DATA SHEET Address Number Mode Function Hex of Bits h’ ACC reference level to adjust C A value of 0 disables the ACC, chroma gain can be adjusted via ACCb / ACCr register. The setting is updated ...
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VPX 3225D, VPX 3224D Address Number Mode Function Hex of Bits h’170 12 r Status of macrovision detection bit [0]: bit [1]: h’171 12 w first line of macrovision detection window h’172 12 w last line of macrovision detection window ...
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PRELIMINARY DATA SHEET Table 6–5: FP-RAM VPX Back-End Address Number Mode Function Hex of Bits h’10f 12 r Position of VACT bit [11:1]: Delay of VACT relative to the trailing edge of HREF h’120 12 w Vertical Begin bit [8:0]: ...
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VPX 3225D, VPX 3224D Address Number Mode Function Hex of Bits h’126 12 w Selection for peaking/coring bit [1:0]: bit [4:2]: bit [5]: bit [6]: bit [7]: bit [8]: bit [11:9]: reserved (must be set to zero) h’127 12 w ...
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PRELIMINARY DATA SHEET Address Number Mode Function Hex of Bits h’11f 12 r Position of VACT bit [11:1]: Delay of VACT relative to the trailing edge of HREF h’12A 12 w Vertical Begin bit [8:0]: bit [11:9]: reserved (must be ...
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VPX 3225D, VPX 3224D Address Number Mode Function Hex of Bits h’130 12 w Selection for peaking/coring bit [1:0]: bit [4:2]: bit [5]: bit [6]: bit [7]: bit [8]: bit [11:9]: reserved (must be set to zero) h’131 12 w ...
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PRELIMINARY DATA SHEET Address Number Mode Function Hex of Bits h’134 12 w Start line even field determines the first line of the VBI-window within even fields (note that lines are counted relative to the whole frame!) h’135 12 w ...
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VPX 3225D, VPX 3224D Address Number Mode Function Hex of Bits h’140 Register for control and latching w bit [1:0]: w bit [2]: w bit [4:3]: w bit [5]: w bit [6]: bit [9]: bit [10]: w ...
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PRELIMINARY DATA SHEET Address Number Mode Function Hex of Bits h’150 12 w Format Selection bit [1:0]: bit [2]: bit [3]: bit [4]: bit [5]: bit [6]: bit [7]: bit [8]: bit [9]: bit [10]: bit [11]: Micronas VPX 3225D, ...
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VPX 3225D, VPX 3224D Address Number Mode Function Hex of Bits h’151 12 w Start position of the programmable ‘video active’ The start position has even value and is given relative to the trailing edge of HREF. ...
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PRELIMINARY DATA SHEET 7. Application Notes 7.1. Differences between VPX 3220A and VPX 322xD The following items indicate the differences between the VPX 322xD and the VPX 3220A: Internal 2 – The control registers (I C and FP-RAM) contain signif- ...
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VPX 3225D, VPX 3224D 7.3.6. Sample Control Code A Windows API function set is provided for controlling the VPX. This API is independent of the actual used ver- sion of the VPX recommended to control the VPX via ...
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PRELIMINARY DATA SHEET 7.5. Typical Application Micronas VPX 3225D, VPX 3224D 85 ...
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VPX 3225D, VPX 3224D 86 PRELIMINARY DATA SHEET Micronas ...
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PRELIMINARY DATA SHEET Micronas VPX 3225D, VPX 3224D 87 ...
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VPX 3225D, VPX 3224D 8. Data Sheet History 1. Preliminary data sheet: “VPX 3225D, VPX 3224D Video Pixel Decoders”, Edition March 5, 1997, 6251-432-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: “VPX 3225D, VPX 3224D Video ...
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Subject: Data Sheet Concerned: Supplement: Edition: New Package for the VPX 3225D–C3, VPX 3224D–C3 1. The VPX 3225D–C3, VPX 3224D–C3 is also available in the PMQFP44 package. 2. The pinning of the PMQFP44 package has been changed, i.e. mirrored vertically. ...
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VPX 3225D, VPX 3224D 1. Specifications 1.1. Outline Dimensions 1 1.75 13.2 Fig. 1–1: 44-Pin Plastic Metric Quad Flat Pack (PMQFP44) Weight approx. 0.4 g Dimensions in mm 1.2. Pin Connections and ...
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PACKAGE INFORMATION Pin No. Pin Name Pin Type 15 B3 OUT 16 B4 OUT 17 B5 OUT 18 B6 OUT 19 B7 OUT 20 VACT OUT 21 LLC OUT 22 OEQ OUT 24 A1 OUT 25 A2 ...
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VPX 3225D, VPX 3224D 1.3. Pin Configuration PIXCLK PVDD PVSS FIELD 34 VREF 35 HREF 36 TDO (DACT, LLC2) 37 TCK 38 VPX 3225D TDI ...