vpx3224d ETC-unknow, vpx3224d Datasheet - Page 35

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
Fig. 2–39: FP register addressing
PRELIMINARY DATA SHEET
2.14. Control Interface
2.14.1. Overview
Communication between the VPX and the external con-
troller is performed serially via the I
SDA).
There are basically two classes of registers in the VPX.
The first class of registers are the directly addressable
I
the hardware. Data written to these registers is inter-
preted combinatorially directly by the hardware. These
registers are all a maximum of 8-bits wide.
The second class of registers are the ‘FP-RAM regis-
ters’, the memory of the onboard microcontroller (Micro-
nas Fast Processor). Data written into this class of regis-
ters is read and interpreted by the FP’s micro-code.
Internally, these registers are 12 bits wide. Communica-
tions with these registers require I
data payloads.
Communication with both classes of registers (I
FP-RAM) is performed via I
telegram depends on which type of register is being ad-
dressed.
2.14.2. I
The VPX has an I
clock synchronization to slow down the interface if re-
quired. The I
dressing. First, the bus address selects the IC, then a
subaddress selects one of the internal registers.
2
Read Address
Write Address
C registers. These are registers embedded directly in
Status
Data
subaddress
2
0
ff
C Bus Interface
space
I
2
2
C
C bus interface uses one level of subad-
2
C bus slave interface and uses I
mcontroller
2
FP
C. The format of the I
2
2
C packets with 16-bit
C bus (pins SCL and
17f
0
FP-RAM
2
C and
2
2
C
C
The I
specification for the fast-mode. It incorporates slope
control for the falling edges of the SDA and SCL signals.
If the power supply of the VPX is switched off, both pins
SCL and SDA float. External pull-up devices must be
adapted to fulfill the required rise time for the fast-mode.
For bus loads up to 200 pF, the pull-up device could be
a resistor; for bus loads between 200 pF and 400 pF, the
pull-up device can be a current source (3 mA max.) or
a switched resistor circuit.
2.14.3. Reset and I
The VPX can respond to one of two possible chip ad-
dresses. The address selection is made at reset by an
externally supplied level on the OE pin. This level is
latched on the inactive going edge of RES.
Table 2–15: I
2.14.4. Protocol Description
Once the reset is complete, the IC is selected by assert-
ing the device address in the address part of a I
mission. A device address pair is defined as a write ad-
dress (86 hex or 8e hex) and a read address (87 hex or
8f hex). Writing is done by sending the device write ad-
dress first, followed by the subaddress byte and one or
two data bytes. For reading, the read subaddress has to
be transmitted, first, by sending the device write address
(86 hex or 8e hex) followed by the subaddress, a second
start condition with the device read address (87 hex or
8f hex), and reading one or two bytes of data. It is not al-
lowed to send a stop condition in between. This will re-
sult in reading erratic data.
The registers of the VPX have 8 or 16 bit data size; 16-bit
registers are accessed by reading/writing two 8-bit data
bytes with the high byte first. The order of the bits in a
data/address/subaddress byte is always MSB first.
Figure 2–40 shows I
operations of the interface; the read operation requires
an extra start condition after the subaddress and repeti-
tion of the read chip address, followed by the read data
bytes. The following protocol examples use device ad-
dress hex 86/87.
OE
0
1
2
C interface of the VPX conforms to the I
A6
1
1
VPX 3225D, VPX 3224D
A5
0
0
2
C bus device addresses
A4
0
0
2
2
C Device Address Selection
C bus protocols for read and write
A3
0
0
A2
0
1
A1
1
1
A0
1
1
R/W
1/0
1/0
2
C trans-
2
C bus
86/87
8e/8f
hex
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