vpx3224d ETC-unknow, vpx3224d Datasheet - Page 81

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
PRELIMINARY DATA SHEET
Address
Hex
h’150
Number
of Bits
12
Mode
w
Format Selection
bit [1:0]:
bit [2]:
bit [3]:
bit [4]:
bit [5]:
bit [6]:
bit [7]:
bit [8]:
bit [9]:
bit [10]:
bit [11]:
Function
Format Selector
00: YUV 4:2:2, ITU-R601
01: YUV 4:2:2, ITU-R656
10: YUV 4:2:2, BStream
Shuffler
0
1
Format of VBI-data (in ITU-R656 mode only!)
Two possibilities are supported to disable the protected
values 0 and 255:
0
1
Note that this selection is applied for lines within the VBI-
window only!
Transmission of VBI-data (in ITU-R656 mode only)
0
1
PIXCLK selection
Setting this bit activates the half-clock mode, in which
PIXCLK is divided by 2 in order to spread the video data
stream
0
1
Disable splitting of text data bytes
During normal operation, sliced teletext bytes are splitted
into 2 nibbles and multiplexed to the luminance and
chrominance part. Setting this bit will disable this splitting.
Sliced teletext data will be output directly on the luminance
path. Note that the limitation of luminance data has to be
disabled with bit [8]. The values 0 and 255 will no longer be
protected in the luminance path!
reserved (must be set to zero)
Disable limitation of luminance data (see bit [6])
0
1
Suppress ITU–R656 headers for blank lines
Change of ITU–R656 header flags
0
1
reserved (must be set to zero)
FP-RAM VPX Back-End
Port A = Y, Port B = UV
Port A = UV, Port B = Y
limitation
7-bit resolution + odd parity LSB
transmit as normal video data
transmit as ancillary data (with ANC-header)
full PIXCLK (normal operation)
PIXCLK divided by 2
enabled
disabled
change header flags in SAV
change header flags in EAV
Formatter
VPX 3225D, VPX 3224D
Default
0
0
0
1
0
0
0
0
0
0
0
Name
format_sel
format
shuf
range
ancillary
halfclk
splitdis
dislim
hsup
flagdel
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