hd61202u Renesas Electronics Corporation., hd61202u Datasheet
hd61202u
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hd61202u Summary of contents
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... Matrix Liquid Crystal GraphicDisplay Column Driver) Description HD61202U is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores the display data transferred from a 8-bit micro controller in the internal display RAM and generates dot matrix liquid crystal driving signals. ...
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... Display data read/write, display on/off, set address, set display start line, read status Lower power dissipation: during display 2 mW max Power supply 2.7V~5.5V CC Liquid crystal display driving voltage 16V CMOS process Ordering Information Type No. Package HD61202UFS 100-pin plastic QFP (FP-100A) HD61202UTE 100-pin thin plastic QFP (TFP-100B) HCD61202U Chip HD61202U 817 ...
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... Y47 26 Y46 27 Y45 28 Y44 29 Y43 30 818 80 DB1 79 DB0 78 GND 77 V4L 76 V3L 75 V2L 74 V1L 73 V EE1 HD61202UFS 66 Y7 (FP-100A Y10 62 Y11 61 Y12 60 Y13 59 Y14 58 Y15 57 Y16 56 Y17 55 Y18 54 Y19 53 Y20 52 Y21 51 Y22 (Top view) ...
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... Y62 9 Y61 10 Y60 11 Y59 12 HD61202UTE Y58 13 (TFP-100B) Y57 14 Y56 15 Y55 16 Y54 17 Y53 18 Y52 19 20 Y51 Y50 21 Y49 22 Y48 23 Y47 24 Y46 25 (Top view) HD61202U 75 V4L 74 V3L 73 V2L 72 Y1L 71 V EE1 Y10 60 Y11 59 Y12 58 ...
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... HD61202U HCD61202U PAD Arrangement No.1 NO.3 CHIP CODE HD61202U NO.27 No.28 HCD61202U Pad Location Coordinates Coordinate PAD PAD PAD No. Name X Y No. ADC –1493 1 1756 26 M –1649 27 2 1756 V 3 –1789 1689 28 CC V4R –1789 1445 29 4 –1789 V3R 1293 5 30 –1789 6 V2R 1148 31 7 V1R – ...
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... Block Diagram M ADC V CC GND V EE1 V EE2 Instruction register Liquid crystal display driver circuit Display data latch Busy Input register Output register flag I/O buffer HD61202U CL FRM RST ø1 ø2 821 ...
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... HD61202U Terminal Functions Terminal Number of Name Terminals I/O Connected Power supply CC GND V 2 Power supply EE1 V EE2 V1L, V1R 8 Power supply V2L, V2R V3L, V3R V4L, V4R $ 3 I MPU $ CS3 MPU R MPU D MPU 822 Functions Power supply for internal logic. ...
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... On/off register 0 set (display off) 2. Display start line register line 0 set (displays from line 0) After releasing reset, this condition can be changed only by instruction. Unused terminals. Don’t connect any lines to these terminals. HD61202U ...
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... HD61202U Function of Each Block Interface Control I/O Buffer: Data is transferred through 8 data bus lines (DB0–DB7). DB7: MSB (most significant bit) DB0: LSB (least significant bit) Data can neither be input nor output unless $ to CS3 are in the active mode. Therefore, when $ to CS3 are not in active mode it is useless to switch the signals of input terminals except #$% and ADC; ...
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... Busy Flag Busy flag = 1 indicates that HD61202U is operating and no instructions except status read instruction can be accepted. The value of the busy flag is read out on DB7 by the status read instruction. Make sure that the busy flag is reset (0) before issuing instructions. D/I R/W E Address Output register ...
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... HD61202U Display On/Off Flip/Flop The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64 state, the display data corresponding to that in RAM is output to the segments. On the other hand, the display data at all segments disappear in off state independent of the data in RAM controlled by display on/off instruction ...
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... X3) COM4 (HD61203U X4) COM5 (HD61203U X5) COM6 (HD61203U X6) COM7 (HD61203U X7) COM8 (HD61203U X8) COM9 (HD61203U X9) COM62 (HD61203U X62) COM63 (HD61203U X63) COM64 (HD61203U X64 Y64 HD61202U pin name 0 1 DB0 (LSB DB1 0 1 DB2 1 0 DB3 1 1 DB4 0 1 DB5 0 1 DB6 ...
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... Figure 3 Relation between RAM Data and Display (cont) 828 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM62 COM63 COM64 HD61202U pin name ...
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... Item Symbol Reset time t RST Do not fail to set the system again because RESET during operation may destroy the data in all the registers except on/off register and in RAM. RST VILC Min Typ Max 1.0 — — t RST Reset timing HD61202U Unit µs 829 ...
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... HD61202U Display Control Instructions Outline Table 3 shows the instructions. Read/write (R/W) signal, data/instruction (D/I) signal, and data bus signals (DB0 to DB7) are also called instructions because the internal operation depends on the signals from the MPU. These explanations are detailed in the following pages. Generally, there are following three kinds of instructions: 1 ...
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... Table 3 Instructions HD61202U 831 ...
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... HD61202U Detailed Explanation Display On/Off Code The display data appears when and disappears when Though the data is not on the screen with remains in the display data RAM. Therefore, you can make it appear by changing into Display Start Line ...
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... RESET = 1 shows that the system is being initialized. In this condition, no instructions except status read can be accepted. RESET = 0 shows that initializing has finished and the system is in the usual operation condition. R/W D/I DB7 DB0 ON Busy 0 OFF RESET MSB LSB HD61202U 833 ...
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... HD61202U COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM60 COM61 COM62 COM63 COM64 Start line = 0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM60 COM61 COM62 COM63 COM64 Start line = 2 Figure 4 Relation between Start Line and Display 834 ...
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... DB7 DB0 to DB7 DB0 to DB7 Figure 5 Address Configuration of Display Data RAM R/W D/I DB7 DB0 MSB LSB R/W D/I DB7 DB0 MSB LSB Y address Page Page Page Page HD61202U 835 ...
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... HD61202U Use of HD61202U Interface with HD61203 (1/64 Duty Cycle V1L, V1R V6 V6L, V6R V5 V5L, V5R V2 V2L, V2R GND V HD61203U CC SHL DS1 DS2 TH CL1 FS M/S FCS STB Power supply circuit + – – – ...
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... Y1 SEG V1 V4 Y64 V3 Selected Non-selected The waveforms Y64 outputs vary with the display data. In this example, the top line of the panel lights up and other dots do not. Figure 6 LCD Driver Timing Chart (1/64 Duty Cycle) HD61202U frame V1 V5 ...
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... HD61202U Interface with CPU 1. Example of Connection with H8/536/S A15 R/W H8/536S RES Figure 7 Example of Connection with H8/536S 838 Decoder CS1 CS2 V CS3 CC A D/I R DB0 to DB7 V CC RST HD61202U ...
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... P10 to P13. Therefore, after enabling the operation by P10 to P13 and specifying D/I signal by P14, read/write from/to the external memory area ($0100 to $01FE) to control HD61202U. In this case, IOS signal is output from SC1 and R/W signal from SC2. For details of HD6800 and HD6801, refer to their manuals. ...
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... COM64 X64 COM65 X1 COM66 X2 COM67 X3 X64 COM128 840 HD61202U HD61202U No Y64 Y1 Y64 COM1 COM2 COM3 LCD panel 128 480 dots Y1 Y64 Y1 Y64 HD61202U HD61202U No. 1 No. 2 Figure 9 Application Example HD61202U No Y32 Y1 Y32 HD61202U No. 8 ...
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... V – – –0 0.3 CC –20 to +75 –55 to +125 and V . EE1 EE2 V3L = V3R V4L = V4R V2L = V2R $ $ , ADC, ø1, ø CS3, E, R/W, D/I, and DB0–DB7. HD61202U Unit Note °C ° 841 ...
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... HD61202U Electrical Characteristics (GND = 0V +75°C) Item Symbol Min Input high voltage VIHC 0.7V VIHT 0.7V 2.0 Input low voltage VILC 0.0 VILT 0.0 0.0 Output high voltage VOH 0.75V 2.4 Output low voltage VOL — — Input leakage current I –1 IL Three-state (off) I –5 TSL input current ...
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... EE –2/7 (V – +2/7 (V – RON Terminal Y (Y1–Y64) – Range of power supply voltage for liquid crystal display drive 5 –V ( Correlation between power supply voltage V –V and HD61202U 16 843 ...
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... HD61202U Terminal Configuration Input Terminal Input/Output Terminal Output Terminal 844 Applicable terminals FRM, CL, RST, ø1, ø2, CS1, CS2, CS3, E, R/W, D/I, ADC PMOS NMOS Applicable terminals: DB0–DB7 V CC (Input circuit) PMOS V CC Enable PMOS NMOS Data NMOS (Output circuit) [three state] Applicable terminals: Y1– ...
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... CYC P P WEL WEH VIHT AS VILT t AS VIHT VILT t DSW VIHT VILT Figure 10 MPU Write Timing HD61202U Unit Note ns Fig. 10, Fig Fig Fig. 11, Fig Fig Fig DHW 845 ...
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... HD61202U E R/W CS1–CS3 D/I DB0–DB7 V = 4.5V to 5.5V CC Test point 90pF Figure 12 DB0–DB7: Load Circuit 846 t CYC P P WEL WEH VIHT t AS VILT VIHT VILT t t DDR VIHT VILT Figure 11 MPU Read Timing V = 2. 2.4k D1 Test point ...
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... WHø WLø D12 D21 VIHC t WHø2 VILC WLø cyc HD61202U Unit Test Condition µs Fig 847 ...
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... HD61202U Display Control Timing (GND = 0V, V Item Symbol FRM delay time t DFRM M delay time low level width t WLCL CL high level width t WHCL CL FRM M Figure 14 Display Control Signal Waveform 848 = 2.7 to 5.5V –20 to +75°C) CC Limit Min Typ Max –2 — +2 –2 — ...