com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 71

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

BALE
nMEMR
A0-A19
nSBHE
D0-D7
D0-D15
nTOPH,
nTOPL
nMEMCS16
(Unlatched)
nMEMCS16
(Latched)
*
**
***
t10
t11
t1
t2
t3
t4
t5
t6
t7
t8
t9
For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address
Mode
130ns minimum inactive time on consective memory reads from the COM90C66.
For Revision D devices, if BALE is tied high, then Address, nSBHE must be held for 20nsec
after nMEMR Low.
or
Address, nSBHE Set Up to BALE Low *
Address, nSBHE Hold after BALE Low *
Address, nSBHE Set Up to nMEMR Low
nMEMR Low to Valid Data
nMEMR Low to nTOPH, nTOPL Low
A19-A17 to nMEMCS16 Low (Unlatched) (128K RAM Decode)
A19-A11 to nMEMCS16 Low (Latched) (2K RAM Decode)
nMEMR High to nTOPH, nTOPL High
nMEMR High to Data High Impedance
nMEMR High to BALE High (Next Address)
Address, nSBHE invalid to nMEMCS16 High
Modified Version of Page 50 for Rev. D COM90C66 Only.
t7
t6
t1
FIGURE 15 - READ RAM CYCLE
t3
Parameter
VALID
t5
t2
t2 ***
71
t4
t11
VALID DATA
min
20
20
25
30
0
0
0
0
0
0
typ max
t9
t10
t8
**
30
40
25
15
80
20
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS