ch7007a Chrontel, ch7007a Datasheet - Page 10

• Manufacturer Part Number: ch7007a
• Description: Ch7007a Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
4.2.4 Flicker Filter and Text Enhancement
The CH7007 integrates an advanced 2-line, 3-line, 4-line and 5-line (depending on mode) vertical deflickering filter
circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive filter
algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both luma
and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates
additional filtering for enhancing the readability of text. These modes are fully programmable via serial port
interface under the flicker filter register.
4.2.5 Internal Voltage Reference
An on chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a
reference resistor at pin ISET, and register controlled divider, sets the output ranges of the DACs. The CH7007
bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal for PAL or NTSC-J,
which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor from ISET
to ground is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for
DAC output is 1/48
equation:
I
For DACG=0, this is: I
For DACG=1, this is: I
4.2.6 Power Management
The CH7007 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off
and Composite Off to provide optimal power consumption for the application involved. Using the programmable
power down modes accessed over the serial port interface, the CH7007 may be placed in either Normal state, or any
of the four power managed states, as listed below (see “Power Management Register” under theRegister
Descriptions section for programming information). To support power management, a TV sensing function (see
“Connection Detect Register” under the Register Descriptions section) is provided, which identifies whether a TV is
connected to either S-Video or composite. This sensing function can then be used to enter into the appropriate
operating state (e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software).
4.3 Luminance and Chrominance Filter Options
The CH7007 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S-
Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown,
the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and
chrominance video bandwidth output is shown in Table 9.
10
LSB
Table 8. Power Management
Operating State
Normal (On):
Power Down:
S-Video Off:
Composite Off:
Full Power Down:
= V(ISET)/ISET reference resistor * 1/GAIN
th
. Therefore, for each DAC, the current output per LSB step is determined by the following
LSB
LSB
= 1.235/360 * 1/48 = 71.4 µ A (nominal)
= 1.317/360 * 1/48 = 76.2 µ A (nominal)
Functional Description
In the normal operating state, all functions and pins are active.
In the power-down state, most pins and circuitry are disabled.The DS/BCO pin
will continue to provide either the VCO divided by K3, or 14.318 MHz out when
selected as an output, and the P-OUT pin will continue to output a clock
reference when in master clock mode.
Power is shut off to the unused DACs associated with S-Video outputs.
In Composite-off state, power is shut off to the unused DAC associated with
CVBS output.
In this power-down state, all but the serial port interface circuits are disabled.
This places the CH7007 in its lowest power consumption mode.
201-0000-002
Rev. 2.95, 6/24/2004
CH7007A