ch7007a Chrontel, ch7007a Datasheet - Page 24

• Manufacturer Part Number: ch7007a
• Description: Ch7007a Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
Flicker Filter Register
The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen
image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker
content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for
the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma
channel filtering includes a setting to enable the chroma dot crawl reduction circuit.
Note: When writing to register O1H, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY
Video Bandwidth Register
24
Table 14. Flicker Filter Settings
VOS[1:0]
Output Format
Bit:
Symbol:
Type:
Default:
FY[1:0]
00
01
10
11
FT[1:0]
00
01
10
11
FC[1:0]
00
01
10
11
Bit:
Symbol:
Type:
[1:0] is bits 1:0 and FT[1:0] is bits 3:2.
7
7
FLFF
R/W
00
PAL
Settings for Luma Channel
Minimal Flicker Filtering
Slight Flicker Filtering
Maximum Flicker Filtering
Invalid
Settings for Text Enhancement Circuit
Maximum Text Enhancement
Slight Text Enhancement
Minimum Text Enhancement
Invalid
Settings for Chroma Channel
Minimal Flicker Filtering
Slight Flicker Filtering
Maximum Flicker Filtering
Enable Chroma DotCrawl Reduction
6
6
CVBW
R/W
5
FC1
R/W
1
5
CBW1
R/W
01
NTSC
4
FC0
R/W
1
4
CBW0
R/W
3
FY1
R/W
0
3
YPEAK
R/W
10
PAL-M
201-0000-002
2
FY0
R/W
0
2
YSV1
R/W
Symbol: FFR
Address: 01H
Bits: 6
Symbol: VBW
Address: 03H
Bits: 8
1
FT1
R/W
1
1
YSV0
R/W
11
NTSC-J
Rev. 2.95, 6/24/2004
CH7007A
0
FT0
R/W
0
0
YCV
R/W