ch7003b-v Chrontel, ch7003b-v Datasheet - Page 14

• Manufacturer Part Number: ch7003b-v
• Description: Ch7003 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
4.3.4 Anti-flicker Filter
The CH7003 integrates an advanced 4-line (3-line for 1:1 modes) vertical deflickering filter circuit to help eliminate
the flicker associated with interlaced displays. When operating in scaled display modes, this flicker circuit provides
an adaptive filter algorithm for implementing flicker reduction with selections of high or low flicker content. When
operating in scale factors other than (1:1) display modes, it provides a selection of high or low flicker content. When
operating in non-scaled (1:1) display modes, it provides a selection of four anti-flicker filter modes (non-filtering
and three levels of flicker filtering). These modes are fully programmable via serial port, and are listed under the
flicker filter register.
4.3.5 Internal Voltage Reference
An on-chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a
reference resistor at pin RSET, and register controlled divider, sets the output ranges of the DACs. The CH7003
bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal (for PAL or NTSC-
J), which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor RSET
is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for DAC
output is 1/48
I
For DACG=0, this is: I
For DACG=1, this is: I
4.3.6 Power Management
The CH7003 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off,
and Composite Off to provide optimal power consumption for the application involved. Using the programmable
power down modes accessed over the serial port, the CH7003 may be placed in either Normal state, or any of the
four power managed states, as listed below (see “Power Management Register” under the Register Descriptions
section for programming information). To support power management, a TV sensing function (see “Connection
Detect Register” under the Register Descriptions section) is provided, which identifies whether a TV is connected to
either
S-Video or composite (or neither). This sensing function can then be used to enter into the appropriate operating
state (e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software).
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Table 12. Power Management
LSB
Operating State
Normal (On):
Power Down:
S-Video Off:
Composite Off:
Full Power Down:
= V(RSET)/RSET reference resistor* 1/GAIN
th
. Therefore, for each DAC, the current output per LSB step is determined by the following equation:
Functional Description
In the normal operating state, all functions and pins are active
In the power-down state, most pins and circuitry are disabled.The BCO
pin will continue to provide either the VCO divided by K3, or 14.318
MHz out.
Power is shut off to the unused DAC’s associated with S-Video
outputs.
In Composite-off state, power is shut off to the unused DAC associated
with CVBS output.
In this power-down state, all but the serial port circuits are disabled.
This places the CH7003 in its lowest power consumption mode.
LSB
LSB
= 1.235/360 * 1/48 = 71.4 A (nominal)
= 1.317/360 * 1/48 = 76.2 A (nominal)
201-0000-023 Rev. 4.2, 4/12/2002
CH7003B