ch7003b-v Chrontel, ch7003b-v Datasheet - Page 25

• Manufacturer Part Number: ch7003b-v
• Description: Ch7003 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
4.7 Transfer Protocol
Both read and write cycles can be executed in “Alternating” and “Auto-increment” modes.
expects a register address prior to each read or write from that location (i.e., transfers alternate between address and
data). Auto-increment mode allows you to establish the initial register location, then automatically increments the
register address after each subsequent data access (i.e., transfers will be address, data, data, data...). A basic serial
port transfer protocol is shown in Figure 20 and described below.
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
3. Upon receiving the first START condition, the CH7003 expects a Device Address Byte (DAB) from the
4. After the DAB is received, the CH7003 expects a Register Address Byte (RAB) from the master. The
Device Address Byte (DAB)
5. After the DAB is received, the CH7003 expects a Register Address Byte (RAB) from the master. The
R/W
Register Address Byte (RAB)
201-0000-023 Rev. 4.2, 4/12/2002
“START” condition. Transitions of address and data bits can only occur while SC is low.
“STOP” condition.
master device. The value of the device address is shown in the DAB data format below.
format of the RAB is shown in the RAB data format below (note that B7 is not used).
format of the RAB is shown in the RAB data format below (note that B7 is not used).
SD
SC
B7
B7
1
1
Condition
Start
AutoInc
B6
B6
1
Read/Write Indicator
“0”:
“1”:
Device ID
1 - 7
master device will write to the CH7003 at the register location specified by the address
AR[5:0]
master device will read from the CH7003 at the register location specified by the
address AR[5:0].
Serial Port
R/W*
Figure 20: Serial Port Transfer Protocol
R/W*=0
AR[5]
B5
B5
8
1
acknowledge
CH7003
ACK
9
AR[4]
B4
B4
0
Data
1 - 8
1
acknowledge
ACK
AR[3]
CH7003
B3
B3
9
1
ADDR*
AR[2]
Data n
B2
B2
1 - 8
acknowledge
CH7003
ACK
9
ADDR
AR[1]
B1
B1
Alternating mode
CH7003B
Condition
AR[0]
R/W
B0
B0
Stop
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