ch7003b-v Chrontel, ch7003b-v Datasheet - Page 4

• Manufacturer Part Number: ch7003b-v
• Description: Ch7003 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
3.2
4
Table 1. Pin Description
44-Pin
PLLC
21-15,
13-12,
10-4
Pin Description
43
41
38
39
30
28
1
3
2
1,44,43,
44-Pin
9,7,6,4,
TQFP
15,14,
13,12,
11,10,
3,2,
42
37
39
41
40
35
32
33
24
22
In/Out
In/Out
Type
Out
Out
Out
In
In
In
In
In
Symbol
D15-D0
XO/FIN
P-OUT
RSET
XCLK
BCO
Y/R
XI
V
H
Digital Pixel Inputs
These pins accept digital pixel data streams with either 8, 12, or 16-bit
multiplexed or 16-bit non-multiplexed formats, determined by the input
mode setting (see Registers and Programming section). Inputs D0 - D7 are
used when operating in 8-bit multiplexed mode. Inputs D0 - D11 are used
when operating in 12-bit mode. Inputs D0 - D15 are used when operating
in 16-bit mode. The data structure and timing sequence for each mode is
described in the section on Digital Video Interface.
Pixel Clock Output
The CH7003, operating in master mode, provides a pixel data clocking
signal to the VGA controller. This pin provides the pixel clock output signal
(adjustable as 1X, 2X or 3X) to the VGA controller (see the section on
Digital Video Interface and Registers and Programming for more details).
The capacitive loading on this pin should be kept to a minimum.
Pixel Clock Input
To operate in a pure master mode, the P-OUT signal should be connected
to the XCLK input pin. To operate in a pseudo-master mode, the P-OUT
clock is used as a reference frequency, and a signal locked to this output (at
1X, 1/2X, or 1/3X the P-OUT frequency) is input to the XCLK pin. To operate
in slave mode, the CH7003 accepts an external pixel clock input at this pin.
The capacitive loading on this pin should be kept to a minimum.
Vertical Sync Input/Output
This pin accepts the vertical sync signal from the VGA controller, or outputs
a vertical sync to the VGA controller. The capacitive loading on this pin
should kept to a minimum.
Horizontal Sync Input/Output
This pin accepts the horizontal sync from the VGA controller, or outputs a
horizontal sync to the VGA controller. The capacitive loading on this pin
should be kept to a minimum.
Buffered Clock Output
This pin provides a buffered output of the 14.31818 MHz crystal input
frequency for other devices and remains active at all times (including
power-down). The output can also be selected to be other frequencies (see
Registers and Programming).
Crystal Input
A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached
between XI and XO/FIN. However, if an external CMOS clock is attached to
XO/FIN, XI should be connected to ground.
Crystal Output or External Fref
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and
XI. An external CMOS compatible clock can be connected to XO/FIN as an
alternative.
Reference Resistor
A 360
RSET and ground. No other connections should be made to this pin.
Luminance Output
A 75
and ground for optimum performance. In normal operating modes other
than SCART, this pin outputs the luma video signal. In SCART mode, this
pin outputs the red signal.
termination resistor with short traces should be attached between Y
resistor with short and wide traces should be attached between
Description
201-0000-023 Rev. 4.2, 4/12/2002
CH7003B