UPD16454AN NEC [NEC], UPD16454AN Datasheet - Page 8

• Manufacturer Part Number: UPD16454AN
• Description: MOS INTEGRATED CIRCUIT
• Manufacturer: NEC [NEC]

Interface with CPU (data transfer)
DR) have 8-bit paths, therefore making it necessary to transfer 4-bit data twice.
upper 4 bits (D4 to D7), then the lower 4 bits (D0 to D3). The busy flag check is performed before the upper 4 bits
are transferred, and is not necessary before transferring the 4 lower bits.
transfer and next transfer (CLK = 1/fc).
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(6) Character generator RAM (CGRAM)
(7) Timing circuit
(8) LCD-related circuit
This LSI interfaces (transfers data) with CPU in 4-bit units (DB0 to DB3), but the internal register circuits (IR and
Assuming that the 8 bits of data are numbered D0 to D7, this data is transferred in the following sequence: first the
If data is transferred without checking BF, taking 10 CLK cycles or more is necessary between previous 8-bit data
CGRAM is a RAM that the user can use to freely define character patterns. Eight types of 5
pattern definitions are possible. The CGRAM address values (character codes) of A10 to A3 in Fig.2 are 00H to
17H (8 types). Other values (line position, output data, etc.) are the same as in Fig.2.
The timing circuit generates timing signals to activate internal circuits. Retrieve timing of RAM needed for
display and internal operation timing through access from the CPU are performed on a time-share basis and
thus do not interfere with each other. Therefore, to change display characters on the LCD panel, even if
DDRAM has been accessed, characters other than those that have been accessed do not flicker.
The LCD driver circuit consists of 14 common signal drivers and 120 segment signal drivers. Each driver is
automatically controlled by an internal control circuit, and outputs a driving waveform corresponding to the
character pattern.
Serial data is always sent from the character pattern of the display data corresponding to the last DDRAM
address, and the character pattern of the display data corresponding to the first DDRAM address (00H) is
latched when inpout in the 120-bit shift register. LCD display positions are shown in Fig.1 of section (4) Display
data RAM (DDRAM).
7-dot character
PD16454A