kac-9630 ETC-unknow, kac-9630 Datasheet - Page 11

• Manufacturer Part Number: kac-9630
• Description: Cmos Image Sensor 126 H X 98 V Ultra Sensitive Global Shutter 580 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Frame Rate Programming
General Operation
A frame is defined as the time it takes to reset every pixel in the
array, integrate the incident light, convert it to digital data and
present it on the digital video port. Figure 12 shows the sensor’s
Master Timer FSM.
For correct operation all frame rate programming registers
should only be updated during array read out.
Integration Time
The integration time is user programmable and is given by:
Where:
Idle Time
The Idle time is the time from the beginning of a frame to the
point that all pixels in the array are reset and the shutter is
opened and as is given by:
www.kodak.com/go/imagers 585-722-4385
N
P
mclk
int
T
is a user programmable delay. This delay is held
in the Integration Time Registers (ITIMEH &
ITIMEL)
is the period of the master clock mclk.
integration
PWRDOWN
T
idle
= (100 * N
= (100 * N
idle
Reset
int
) * P
+2) * P
OPEN SHUTTER
CLOSE SHUTTER
INTEGRATE
mclk
SHIFTOUT
HBLANK
mclk
IDLE
Count 128/1024
Figure 12: Master Timer FSM
Count 100
Count 40
Repeat N
Repeat 101
11
Iint
Where:
Idle time is only used in video mode.
Read Out Time
The time it will take to readout a complete frame including the
row of black pixels is given by:
Where:
Frame Rate
The frame rate in frames per second is given by:
Note: Integration (N
grammed at any time but will not take effect until the next frame.
Video Mode
N
P
σ
The horizontal blanking time is 40 clocks.
idle
mclk
Snapshot Mode
Notes:
•
•
T
readout
F
rate
is a user programmable delay. This delay is held
in the Idle Time Register (IDLE).
is the period of the master clock mclk.
is 1 when the digital image data port is operating
in parallel mode and 8 when the digital image
data port is operating in serial mode.
Gain values programmed in the VGAIN register
are only applied to the internal video gain
amplifier during the horizontal blanking period
(state: HBLANK).
Idle and integration time values programmed in
the ITIMEL, ITIMEH and IDLE registers are
only applied to Master Timer FSM during the
IDLE state.
=
= (128 *
int
T
) and Idle (N
idle
Exit idle state if
triggered externally
IDLE
IDLE
+ T
σ
integration
+ 40) * 101 * P
Count 100
Repeat N
1
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idle
+ T
) delays can be pro-
readout
idle
mclk