kac-9638 ETC-unknow, kac-9638 Datasheet - Page 17

• Manufacturer Part Number: kac-9638
• Description: Kodak Kac-9638 Cmos Image Sensor
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
6.4
Full frame integration is when each pixel in the array integrates
light incident on it for the duration of a frame (see Figure 27).
The number of pixels processed per row is given by:
Where:
The number of Hclk clock cycles required to process & shift out
one row of pixels is given by:
Where:
The number of rows in the active window is given by:
Where:
.
KAC-9638
WEndCol
WStartCol
MH
R
R
N
R
www.kodak.com/go/imagers 585-722-4385
opcycle
Itime
pix
delay
factor
Row n
Full Frame Integration
N
N
rows
is the “Active Window” column end address as pro-
grammed in registers WCOLE and WCOLLSB.
is the “Active Window” column start address as pro-
grammed in registers WCOLS and WCOLLSB.
Is 1 when horizontal subsampling is disabled and 0.5
when horizontal subsampling is enabled.
is a fixed integer value of 140 representing the Row
Operation Cycle Time in multiples of Hclk clock
cycles. It is the time required to carry out all fixed row
operations outlined in Figure 24.
When partial frame integration is enabled, (PrtFrmEn
bit in the ITIMECONFIG register is set to a logic 1),
R
gration is disabled, (PrtFrmEn bit in the ITIMECON-
FIG register is set to a logic 0), R
Is the number of pixels processed in a row.
a programmable value between 0 & 8191 represent-
ing the Row Delay Time in multiples of Hclk. This
parameter allows the Row Operation Cycle time to be
extended. The Rdelay value is programmed in the
RDELAYH and RDELAYL registers.
pix
RN
Itime
= (WEndCol - WStartCol + 1) * MH
Hclk
= (WEndRow - WStartRow + 1)*MV
Frame
is a fixed integer of 34. When Partial frame inte-
Delay
= R
opcycle
Row 0
+ R
Itime
Row 1
(continued)
+ N
Programmable Row Delay
Programmable Row Delay
pix
Figure 27. Partial and Full Frame Integration
Itime
+ R
Row 2
is 0.
delay
factor
factor
Partial Frame Integration
Full Frame integration
Full Integration Time
17
Row x
Row CDS, Reset Row x+∆ & Shift
Row CDS, Reset Row x & Shift
WEndRow
is the “Active Window” row start address as programmed in reg-
WStartRow
MV
The number of Hclk clocks required to process a full frame is
given by:
Where:
N
F
The frame rate is given by:
6.5
In some cases it is desirable to reduce the time during which the
pixels in the array are allowed to integrate incident light without
changing the frame rate.
This is known as Partial Frame Integration and can be achieved
by resetting pixels in a given row ahead of the row being
selected for readout as shown in Figure 27. The number of Hclk
clocks required to process a partial frame is given by:
Where:
RN
Itime
Note:
Upon system reset the partial frame integration is automatically
enabled. It can be disabled by setting the PrtFrmEn bit in the
ITIMECONFIG register to a logic 0 or by programming 0.
delay
rows
Hclk
factor
Partial Integration
Partial Frame Integration
Time
isters WROWE and WROWLSB.
is the “Active Window” row start address as pro-
grammed in registers WROWS and WROWLSB.
Is 1 when vertical subsampling is disabled and 0.5
when vertical subsampling is enabled.
is the number of rows in the “Active Window”.
a programmable value between 0 & 32767 represent-
ing the Inter Frame Delay in multiples of RN
parameter allows the frame time to be extended. (See
the Frame Delay High and Frame Delay Low regis-
ters). The Fdelay value is programmed in the FDE-
LAYH and FDELAYL registers.
is the number of Hclk clock cycles required to process
& shift out one row of pixels.
a programmable value between 0 & 32767 represent-
ing the number of rows ahead of the current row to be
reset. The Itime value is programmed in the ITIMEH
and ITIMEL registers.
FN
Hclk
FP
Row x+∆ Row n
= [N
Frame Rate =
Hclk
rows
= RN
+ Fdelay]
Hclk *
FN
Hclk
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Itime
Hclk
*
Frame
Delay
RN
Hclk
Row 0
Hclk
. This