UPD65 NEC [NEC], UPD65 Datasheet - Page 17

• Manufacturer Part Number: UPD65
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
• Manufacturer: NEC [NEC]

3.2.4 S
mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled
(bit 3 of P4 register is set to 0), it can be used as the input port which does not release the STOP mode even if
the release condition is established (at this time, a pull-down resistor is not connected internally.)
state.
3.3 Control Register 0 (P3)
The S
Use of the STOP mode release of the S
When using the pin as a key input from a key matrix, enable (bit 3 of P4 register is set to 1) the use of the STOP
The state of the pin can be read in both cases.
At reset, the pin is set to INPUT mode where the STOP mode release is disabled, and goes to high-impedance
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.
When reset, the register becomes 0000 0011B.
b
b
b
b
Note Set DP
Remark
0
2
3
4
, b
, b
2
1
5
, b
2
port (bit 1 of P1)
: These bits specify the carrier frequency and duty ratio of the REM output.
: This bit specifies the availability of the carrier of the frequency specified by b
: This bit changes the carrier frequency and the timer clock’s frequency division ratio.
port is an input port.
Bit
Name
Set
value
When reset 0
6
“0” = ON (with carrier); “1” = OFF (without carrier; high level)
“0” = 1/1 (carrier frequency: the specified value of b
“1” = 1/2 (carrier frequency: half of the specified value of b
: These bits specify the high-order 3 bits (DP
: don’t care
0
0
10
b
3
of the PD64A to "0".
0
1
0
1
0
1
b
Fixed
to “0”
0
7
b
—
2
Table 3-5. Timer Clock and Carrier Frequency Setup
0
0
1
1
0
0
1
1
b
DP
0
1
0
b
6
1
10
Table 3-4. Control Register 0 (P3)
Note
DP (Data pointer)
0
1
0
1
0
1
0
1
2
b
port can be specified by bit 3 of the P4 register.
b
DP
0
1
0
0
Data Sheet U14380EJ2V0DS00
5
9
f
f
X
X
/64
/128
Timer Clock
b
DP
0
1
0
4
8
8
, DP
0
9
b
1/1
1/2
0
TCTL
3
and b
and DP
Carrier Frequency (Duty Ratio)
f
f
f
f
Without carrier (high level)
f
f
f
f
Without carrier (high level)
0
1
X
X
X
X
X
X
X
X
; timer clock: f
/8 (Duty 1/2)
/64 (Duty 1/2)
/96 (Duty 1/2)
/96 (Duty 1/3)
/16 (Duty 1/2)
/128 (Duty 1/2)
/192 (Duty 1/2)
/192 (Duty 1/3)
and b
10
b
CARY
ON
OFF
0
) of ROM’s data pointer.
2
1
; timer clock: f
b
MOD
Refer to Table 3-5.
1
1
X
/64)
1
0
and b
X
b
MOD
1
/128)
0
PD64A, 65
1
.
0
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