DS2182 DALLAS [Dallas Semiconductor], DS2182 Datasheet - Page 14

• Manufacturer Part Number: DS2182
• Description: T1 Line Monitor
• Manufacturer: DALLAS [Dallas Semiconductor]

is established using the FT information, while multiframe sync is established only if valid FS information
is present. If no valid FS pattern is identified, the synchronizer moves to the FT alignment, RLOS goes
low, and a false multiframe position may be indicated by RMSYNC. RFER indicates when the received
S-bit pattern does not match the assumed internal multiframe alignment. This mode will be used in
applications where non-standard S-bit patterns exist. In such applications, multiframe alignment
information can be decoded externally by using the S-bits present at RLINK.
SYNC TIME (RCR1.2)
Bit RCR1.2 determines the number of consecutive framing pattern bits to be qualified before SYNC is
declared. If RCR1.2 =1, the algorithm validates 24 bits; if RCR1.2 = 0, 10 bits are validated. Validating
24 bits results in superior false framing protection while 10-bit testing minimizes reframe time. In either
case, the synchronizer only establishes resync when one and only one candidate is found (see Table 5).
AVERAGE REFRAME TIME Table 5
NOTE:
1. Average reframe time is defined here as the average time it takes from the start of resync (rising edge
SYNC ENABLE (RCR1.1)
When RCR1.1 is cleared, the receiver initiates automatic resync if an OOF event occurs or if carrier loss
(192 consecutive 0s) occurs (depends on RCR1.7). When RCR1.1 is set, the automatic resync circuitry is
disabled. In this case, resync can only be initiated by setting RCR1.0 to 1 or externally transitioning
from low to high. Note that using
of RCR1.1 will not affect the output timing until the new alignment is located.
RESYNC (RCR1.0)
A 0-to-1 transition of RCR1.0 causes the synchronizer to search for the framing pattern sequence
immediately, regardless of the internal sync status. In order to initiate another resync command, this bit
must be cleared and then set again.
FRAME
of RLOS) to the actual loading of the new alignment (on a multiframe edge) into the output receive
timing.
MODE
193S
193E
3.0ms
6.0ms
MIN
RCR1.2=0
3.75ms
RST
AVG.
7.5ms
to initiate a resync resets the output timing while
14 of 25
MAX.
4.5ms
9.0ms
13.0ms
6.5ms
MIN.
RCR1.2=1
7.25ms
14.5ms
AVG.
RST
is low; use
16.0ms
MAX
8.0ms
DS2182A
RST