ch7301c Chrontel, ch7301c Datasheet - Page 16

• Manufacturer Part Number: ch7301c
• Description: Ch7301 Dvi Transmitter
• Manufacturer: Chrontel

CHRONTEL
Bit 3 of register GPIO resets the hot plug detection circuitry. A value of ‘1’ causes the CH7301C to release the
GPIO[1]/HPINT pin. When a hot plug interrupt is asserted by the CH7301C, the CH7301C driver should read the
DVIT bit in register 20h to determine the state of the DVI termination. After having read this, the HPIR bit should
be set high to reset the circuit, and then set low again. In order to reset the HPIR bit high, DVIP and DVIL bits of
register 49h[7:6] must first be set to ’11’.
Bits 5-4 of register GPIO defines the GPIO Read or Write Data bits [1:0]. When the corresponding GOENB bits
(GOENB[1:0]) are ’0’, the values in GPIOL[1:0] are driven out at the corresponding GPIO pins. When the
corresponding GOENB bits are ’1’, the values in GPIOL[1:0] can be read to determine the level forced into the
corresponding GPIO pins.
Bits 7-6 of register GPIO are GPIO Direction Control bits [1:0]. GOENB[1:0] control the direction of the
GPIO[1:0] pins. A value of ‘1’ sets the corresponding GPIO pin to an input, and a value of ‘0’ sets the
corresponding pin to a non-inverting output. The level at the output depends on the value of the corresponding bit
GPIOL[1:0].
Input Data Format Register
Bits 2-0 of register IDF select the input data format. See Input Interface on section 3.3 on page 8 for a listing of
available formats.
HSP (bit 3) of register IDF controls the horizontal sync polarity. A value of ’0’ defines the horizontal sync to be
active low, and a value of ’1’ defines the horizontal sync to be active high.
VSP (bit 4) of register IDF controls the vertical sync polarity. A value of ’0’ defines the vertical sync to be active
low, and a value of ’1’ defines the vertical sync to be active high.
DES (bit 6) of register IDF signifies when the CH7301C is to decode embedded sync signals present in the input
data stream instead of using the H and V pins. This feature is only available for input data format #4. A value of ’0’
selects the H and V pins to be used as the sync inputs, and a value of ’1’ selects the embedded sync signal.
Connection Detect Register
The Connection Detect Register provides a means to determine the status of the DAC outputs and the DVI hot plug
16
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
Reserved
HPIE Reserved
R/W
R/W
7
1
7
0
DES Reserved
R/W
R/W
6
0
6
0
DVIT Reserved
R/W
R
5
0
5
0
R/W
VSP
R/W
4
0
4
0
DACT2
R/W
HSP
X
R
3
0
3
201-0000-056
DACT1
IDF2
R/W
Symbol:
Address:
Symbol:
Address:
X
R
2
0
2
DACT0
Rev. 1.32,
IDF1
R/W
CH7301C
X
R
1
0
1
IDF
1Fh
CD
20h
5/24/2005
SENSE
IDF0
R/W
R/W
0
0
0
0