ch7301c Chrontel, ch7301c Datasheet - Page 19

• Manufacturer Part Number: ch7301c
• Description: Ch7301 Dvi Transmitter
• Manufacturer: Chrontel

CHRONTEL
DVI PLL Charge Pump Control Register
Bit 0 of register TPCP control the DVI PLL charge pump.
Bits 3-2 of register TPCP control the DVI PLL post scale divider. The value should be set as shown in Table 10
depending on the input frequency range.
Bit 4 of register TPCP inverts the DVI outputs. A value of 1 inverts the output. A value of 0 is recommended.
Bits 7-5 of register TPCP control the DVI transmitter output drive level. The value should be set as shown in Table
10.
DVI PLL Divider Register
Bits 3-0 of register TPD control the DVI PLL feedback divider. The default value is recommended.
Bits 5-4 of register TPD control the DVI PLL feed forward divider. The default value is recommended.
Please see Table 10 for the default values in terms of the frequency ranges.
DVI PLL Supply Control Register
This register controls the voltage in the DVI PLL, use default settings for this register.
201-0000-056
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
Reserved Reserved TPFFD1 TPFFD0 TPFBD3 TPFBD2 TPFBD1
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
DVID2
Rev. 1.32,
R/W
R/W
R/W
7
1
7
0
7
0
DVID1
5/24/2005
R/W
R/W
R/W
6
1
6
0
6
0
DVID0
R/W
R/W
R/W
5
1
5
0
5
1
DVII TPPSD1 TPPSD0 Reserved
R/W
R/W
R/W
4
0
4
1
4
1
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
Symbol:
Address:
Symbol:
Address:
Symbol:
Address:
2
1
2
1
2
0
R/W
R/W
R/W
CH7301C
1
0
1
1
1
0
TPCP
33h
TPD
34h
TPVT
35h
Reserved
TPFBD0
TPCP0
R/W
R/W
R/W
19
0
0
0
0
0
0