ch7304 Chrontel, ch7304 Datasheet - Page 11

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
The power up sequence can occur only if (a) XCLK is not missing, (b) there are no missing HSYNC and VSYNC, (c)
the PLL CLOCK is stable, and (d) PANEN is set to 1. The power down sequence happens if any of those conditions fails.
The power up sequence can also occur if the panel protection circuitry is bypassed.
The panel protection circuitry is comprised of a LOCKDET block, which detects an unstable clock from the LVDS PLL,
a SYNCDET block, which detects missing inputs HSYNC and VSYNC and an XCLK Detect block which detects
missing XCLK. XCLK stability (assuming it is not missing) is determined by the number of PLL unlock signals
generated within one frame. This number is programmable via serial port using the BGLMT register (Register 7Fh).
The SYNCDET block consists of counters to count HSYNC and VSYNC pulses. One counter is used to count the
number of HSYNC pulses per frame over 3 frames. The end counts for all 3 frames must be equal to enable the power up
sequence. In addition, the SYNCDET block checks for the presence of VSYNC and HSYNC. If VSYNC is missing for 2
frames or if HSYNC is missing for 32us the power up sequence is disabled.
The XCLK Detect block detects if XCLK is missing for more than approximately 1.2us.
201-0000-053
Rev. 1.31, 6/14/2006
XCLK
FOSC (from oscillator)
HSYNC
VSYNC
LSYNCEN
FIFO
Detect
XCLK
DETECT
LVDS
PLL
SYNC
Figure 6: Detection Circuits for Panel Protection
XCLK
LOCK
Reg. 14h [2]
Power Sequencing
CLKDETD
DETECT
LOCK
XCLK
Register 66h
LSYNCEN
LPFORC
SYNCST
LPLOCK
PANEN
LPLEN
BKLEN
LOCKST
LPFORC
LPLEN
Note:
1) LOCKST will be logic
low if either XCLK or the
LVDS PLL output is
unstable.
2) SYNCST will be logic
low if either Hsync or
Vsync is unstable or
missing.
0
1
MUX
ENAVDD
ENABKL
CH7304
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