ch7304 Chrontel, ch7304 Datasheet - Page 6

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
2.0 Functional Description
2.1
2.1.1
Two distinct methods of transferring data to the CH7304 are described. They are:
For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7304 is latched with both edges of the clock
(also referred to as dual edge transfer mode or DDR). For the multiplexed data, clock at 2X pixel rate the data applied to
the CH7304 is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the
pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is
programmable. In dual edge transfer modes, the clock edge used to latch the first half of each pixel is programmable.
2.1.2
The graphics controller interface can operate at a variable voltage level controlled by the voltage on the VDDV pin. This
should be set to the maximum voltage of the interface (typically 3.3V or adjustable between 1.1 and 1.8V). The VREF
pin is the voltage reference for the data, data enable, clock and sync inputs and must be tied to VDDV/2. This is typically
done using a resistor divider.
2.1.3
Figure 3 shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform represents the input
clock for single edge transfer (SDR) methods. The second XCLK/XCLK* waveform represents the input clock for the
dual edge transfer (DDR) method. The timing requirements are given in Section 4.5.
6
2X
1X
•
•
Input Data Formats
Overview
Multiplexed data, clock input at 1X the pixel rate
Multiplexed data, clock input at 2X the pixel rate
Interface Voltage Levels
Input Clock and Data Timing Diagram
XCLK/
XCLK*
XCLK/
XCLK*
D[15:0]
H
V
Figure 3: Clock, Data and Interface Timing
64 pixels
1 VGA Line
201-0000-053
Rev. 1.31,
CH7304
6/14/2006