DS1244W-120 DALLAS [Dallas Semiconductor], DS1244W-120 Datasheet - Page 3

• Manufacturer Part Number: DS1244W-120
• Description: 256k NV SRAM with Phantom Clock
• Manufacturer: DALLAS [Dallas Semiconductor]

RAM READ MODE
The DS1244 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable)
is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the
32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within t
(access time) after the last address input signal is stable, providing that CE and OE (output enable)
access times and states are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t
RAM WRITE MODE
The DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (t
during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE
active) then WE will disable the outputs in t
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when V
However, when V
internal clock registers and SRAM are blocked from any access. When V
point, V
operation and SRAM data are maintained from the battery until V
The 3.3V device is fully accessible and data can be written or read only when V
When V
power is switched from V
than V
V
levels.
All control, data, and address signals must be powered down when V
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of the chip enable, output enable, and write enable. Initially, a read cycle to any memory location using
CE or t
BAT
. RTC operation and SRAM data are maintained from the battery until V
WR
BAT
OE
SO
CC
) before another cycle can be initiated. The OE control signal should be kept inactive (high)
, the device power is switched from V
for OE , rather than address access.
(battery supply level), device power is switched from the V
fall as below the V
CC
is below the power fail point, V
CC
to the backup supply (V
PF
, access to the device is inhibited. If V
ODW
from its falling edge.
CC
to the backup supply (V
3 of 19
BAT
PF
) when V
(point at which write protection occurs), the
CC
CC
is returned to nominal levels.
CC
drops below V
CC
is powered down.
CC
PF
pin to the backup battery. RTC
falls below the battery switch
is less than V
BAT
CC
) when V
CC
is returned to nominal
CC
is greater than V
is greater than V
PF
. If V
CC
BAT
drops below
, the device
PF
is greater
CO
ACC
for
PF
PF
.
.