DS14285-DS14287 DALLAS [Dallas Semiconductor], DS14285-DS14287 Datasheet - Page 4

• Manufacturer Part Number: DS14285-DS14287
• Description: Real Time Clock with NV RAM Control
• Manufacturer: DALLAS [Dallas Semiconductor]

R/
connected to V
read or write. A read cycle is indicated with a high level on R/
indicated when R/
When the MOT pin is connected to GND for Intel timing, the R/
RAMs.
DS14285/DS14287 to be accessed.
and during
addresses but no access will occur. When V
inhibits access cycles by internally disabling the
data and RAM data during power outages.
can be used as an interrupt input to a processor. The
causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the
processor program normally reads the C register. The
When no interrupt conditions are present, the
interrupting devices can be connected to an
external pull-up resistor.
that
time
DS14285/DS14287 on power-up has timed out. When
following occurs:
CS
IRQ
RESET
RESET
WR
W
. In this mode the R/
(Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the
RESET
(Interrupt Request Output) - The
RESET
(Read/Write Input) - The R/
pin can be held low for a time in order to allow the power supply to stabilize. The amount of time
(Reset Input) - The
RD
is held low is dependent on the application. However, if
is low should exceed 200 ms to make sure that the internal timer that controls the
A. Periodic Interrupt Enable (PEI) bit is cleared to 0.
B. Alarm Interrupt Enable (AIE) bit is cleared to 0.
C. Update Ended Interrupt Flag (UF) bit is cleared to 0.
D. Interrupt Request Status Flag (IRQF) bit is cleared to 0.
E. Periodic Interrupt Flag (PF) bit is cleared to 0.
F. The device is not accessible until
G. Alarm Interrupt Flag (AF) bit is cleared to 0.
H.
I. Square Wave Output Enable (
J. Update Ended Interrupt Enable (UIE) is cleared to 0.
K.
CC
and
for Motorola timing, R/
W
IRQ
CEO
WR
is low during DS.
pin is in the high impedance state.
is driven high.
for Intel timing. Bus cycles which take place without asserting
W
RESET
pin has the same meaning as the Write Enable signal (
pin has no effect on the clock, calendar, or RAM. On power-up the
CS
W
must be kept in the active state during DS for Motorola timing
pin also has two modes of operation. When the MOT pin is
IRQ
W
IRQ
is at a level which indicates whether the current cycle is a
CC
pin is an active low output of the DS14285/DS14287 that
bus. The
SQWE
is below 4.25 volts, the DS14285/DS14287 internally
CS
IRQ
4 of 25
RESET
input. This action protects both the real time clock
RESET
) bit is cleared to 0.
IRQ
level is in the high impedance state. Multiple
RESET
IRQ
is returned high.
output remains low as long as the status bit
pin also clears pending interrupts.
bus is an open drain output and requires an
is low and V
W
W
signal is an active low signal called
while DS is high. A write cycle is
RESET
CC
is used on power-up, the
is above 4.25 volts, the
WE
DS14285/DS14287
CS
) on generic
IRQ
will latch
pin the