DS17285-DS17287 DALLAS [Dallas Semiconductor], DS17285-DS17287 Datasheet

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... RAM clear input § Century register § Date alarm register § Compatible with existing BIOS for original DS1287 functions § Available as chip (DS17285) or standalone module with embedded battery and crystal (DS17287) § Timekeeping algorithm includes leap-year compensation valid up to 2100 § ...

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... The DS17285/DS17287 are real-time clocks (RTCs) designed as successors to the industry standard DS1285, DS1385, DS1485, DS1585, and DS1685 PC real-time clocks. These devices provide the industry standard DS1285 clock function with either +3V or +5V operation. The DS17285 also incorporates a number of enhanced features including a silicon serial number, power-on/off control circuitry, 114 bytes of user NV SRAM plus 2kB of additional NV RAM, and 32 ...

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... RAM access time. Addresses must be valid prior to the latter portion of ALE, at which time the DS17285/DS17287 latches the address. Valid write data must be present and held stable during the latter portion of the ...

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... However, no data transfer occurs. – Interrupt Request Output; Open Drain, Active Low. The IRQ the DS17285/DS17287 that can be tied to the interrupt input of a processor. The as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the ...

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Figure 1. BLOCK DIAGRAM ...

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... DS17285 ONLY X1, X2 – Connections for a standard 32.768kHz quartz crystal. For greatest accuracy, the DS17285 must be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal select (CS) bit in extended-control register 4B is used to select operation with a 6pF or 12.5pF crystal. The crystal is attached directly to the X1 and X2 pins ...

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... RTC ADDRESS MAP The address map for the RTC registers of the DS17285/DS17287 is shown in Figure 2. The address map consists of the 14 clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and 4 bytes are used for control and status. All registers can be directly written or read except for the following: 1) Registers C and D are read-only ...

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The three time alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the ...

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CONTROL REGISTERS The four control registers and D reside in both bank 0 and bank 1. These registers are accessible at all times, even during the update cycle. REGISTER A MSB BIT 7 BIT 6 UIP DV2 ...

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... PF bit is still set at the IRQ periodic rate. PIE is not modified by any internal DS17285/DS17287 functions. AIE – Alarm Interrupt Enable. The AIE bit is a read/write bit which, when set permits the alarm flag (AF) bit in Register C to assert bytes equal the three alarm bytes, including a “ ...

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REGISTER C MSB BIT 7 BIT 6 IRQF PF IRQF – Interrupt Request Flag. This bit is set when one or more of the following are true: i.e., IRQF = (PF x PIE) + (AF x AIE) ...

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... NV RAM–RTC The general-purpose NV RAM bytes are not dedicated to any special function within the DS17285/DS17287. They can be used by the application program as nonvolatile memory and are fully available during the update cycle. The user RAM is divided into two separate memory banks. When the bank 0 is selected, the 14 real-time clock registers and 114 bytes of user RAM are accessible ...

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... Therefore, IRQ determination that the DS17285/DS17287 initiated an interrupt is accomplished by reading Register C and finding IRQF = 1. IRQF remains set until all enabled interrupt flag bits are cleared to 0. OSCILLATOR CONTROL BITS When the DS17287 is shipped from the factory, the internal oscillator is turned off ...

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Table 2. PERIODIC INTERRUPT RATE AND SQUARE-WAVE OUTPUT FREQUENCY EXTENDED SELECT BITS REGISTER A REGISTER B E32k RS3 RS2 ...

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UPDATE CYCLE The serialized RTC executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, alarm, ...

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... RAM are in the same locations as for the DS1287 result, existing routines implemented within BIOS, DOS, or application software packages can gain access to the DS17285/DS17287 clock registers with no changes. Also in bank 0, an extra 64 bytes of RAM are provided at addresses just above the original locations for a total of 114 directly addressable bytes of user RAM ...

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... B, 0BH). When the match condition occurs, the This output can be used to turn on the main system power supply that provides V DS17285/DS17287 as well as the other major components in the system. Also at this time, the wake-up flag (WF, bank 1, register 04AH) is set, indicating that a wake-up condition has occurred. ...

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... Wake-Up/Kickstart Timing Diagram in the Electrical Specifications section of this data sheet. The timing associated with these functions is divided into five intervals, labeled the diagram. The occurrence of either a kickstart or wake-up condition causes the described above. During interval 1, if the supply voltage on the DS17285/DS17287 V the greater ...

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... PRS = 0 RAM Clear The DS17285/DS17287 provides a RAM clear function for the 114 bytes of user RAM. When enabled, this function can be performed regardless of the condition of the V The RAM clear function is enabled or disabled through the RAM clear-enable bit (RCE; bank 1, register 04BH) ...

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... Figure 4. DS17285/DS17287 EXTENDED REGISTER BANK DEFINITION BANK 0 MSB DV0 = 0 00 TIMEKEEPING AND CONTROL BYTES - USER RAM BYTES - USER RAM 7F LSB MSB 00 TIMEKEEPING AND CONTROL BYTES - USER RAM 3F 40 MODEL NUMBER BYTE 41 1ST BYTE SERIAL NUMBER 42 2ND BYTE SERIAL NUMBER ...

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... EXTENDED CONTROL REGISTERS Two extended control registers are provided to supply controls and status information for the extended features offered by the DS17285/DS17287. These are designated as extended control registers 4A and 4B and are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits within these registers are described as follows ...

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... CS RCE PRS and the RAM clear function are disabled. RCLR pin is set high-z when the DS17285 goes into power PWR pin remains active upon entering power fail. voltage is absent and WIE is set the CC voltage is absent and KSE is set the CC pulsed low), causing the KF bit to be set to 1 ...

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SYSTEM MAINTENANCE INTERRUPT (SMI) RECOVERY STACK An SMI recovery register stack is located in the extended register bank, locations 4Eh and 4Fh. This register stack, shown below, can be used by the BIOS to recover from an SMI occurring during ...

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ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground Storage Temperature Range Soldering Temperature Range * This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in ...

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DC ELECTRICAL CHARACTERISTICS PARAMETER Average V Power Supply CC Current CMOS Standby Current ( = V - 0.2V Input Leakage Current (Any Input) Output Leakage Current Output Logic 1 Voltage (I = -1.0mA) OUT Output Logic 0 Voltage ...

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DC ELECTRICAL CHARACTERISTICS PARAMETER Average V Power-Supply CC Current CMOS Standby Current ( = V - 0.2V Input Leakage Current (Any Input) Output Leakage Current Output Logic 1 Voltage at -0.6mA Output Logic 0 Voltage at +1.2mA Power-Fail ...

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RTC AC TIMING CHARACTERISTICS PARAMETER Cycle Time Pulse-Width, / Low RD WR Pulse-Width, / High RD WR Input Rise and Fall Chip-Select Setup Time Before Chip-Select Hold Time Read Data Hold Time Write Data Hold Time Muxed ...

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RTC AC TIMING CHARACTERISTICS PARAMETER Cycle Time Pulse-Width, / Low RD WR Pulse-Width, / High RD WR Input Rise and Fall Time Chip-Select Setup Time before Chip-Select Hold Time Read Data Hold Time Write Data Hold Time ...

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BUS TIMING FOR READ CYCLE TO RTC AND RTC REGISTERS BUS TIMING FOR WRITE CYCLE TO RTC AND RTC REGISTERS ...

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POWER-UP/POWER-DOWN TIMING, 5V PARAMETER High to Power-Fail CS Recovery at Power-Up V Slew Rate Power-Down CC V Slew Rate Power-Down CC V Slew Rate Power-Up CC Expected Data Retention POWER-UP/POWER-DOWN TIMING, 3V PARAMETER High to Power-Fail CS Recovery at Power-Up ...

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POWER-UP CONDITION, 3V POWER-DOWN CONDITION ...

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POWER-UP CONDITION, 5V POWER-DOWN CONDITION ...

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WAKE-UP/KICKSTART TIMING Note: Time intervals shown above are referenced in Wake-Up/Kickstart section. *This condition can occur with the 3V device ...

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... I are measured at V BAT1 BAT2 (DS17285). 12) RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post- solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used ...

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... DS17285 24-PIN DIP PKG 24-PIN DIM MIN MAX A IN 1.245 1.270 MM 31.62 32. 0.530 0.550 MM 13.46 13. 0.140 0.160 MM 3.56 4. 0.600 0.625 MM 15.24 15. 0.015 0.050 MM 0.380 1. 0.120 0.145 MM 3.05 3. 0.090 0.110 MM 2.29 2. 0.625 0.675 MM 15.88 17. 0.008 0.012 MM 0.20 0. 0.015 0.022 MM 0.38 0. ...

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... DS17285 24-PIN SO The chamfer on the body is optional not present, a terminal 1 identifier must be positioned so that one-half or more of its area is contained in the hatched zone. PKG 24-PIN DIM MIN MAX A IN 0.094 0.105 MM 2.38 2. 0.004 0.012 MM 0.102 0. 0.089 0.095 MM 2.26 2. 0.013 0.020 MM 0 ...

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... DS17285 28-PIN TSOP PKG 28-PIN DIM MIN MAX A — 1.20 A1 0.05 — A2 0.91 1.02 b 0.18 0.27 c 0.15 0.20 D 13.20 13.60 D1 11.70 11.90 E 7.90 8.10 e 0.55 BSC L 0.30 0.70 L1 0.80 BSC 56-G5003-000 ...

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DS17287 RTC PLUS RAM Note: Pins 2, 3, 16, and 20 are missing by design. PKG 24-PIN DIM MIN MAX A IN 1.320 1.335 MM 33.53 33. 0.720 0.740 MM 18.29 18. 0.345 0.370 MM 8.76 ...