DS17885-DS17887 DALLAS [Dallas Semiconductor], DS17885-DS17887 Datasheet - Page 22

• Manufacturer Part Number: DS17885-DS17887
• Description: 3V/5V Real-Time Clock
• Manufacturer: DALLAS [Dallas Semiconductor]

EXTENDED CONTROL REGISTER 4B
ABE – Auxiliary Battery Enable. This bit when written to a logic 1 enables the V
functions.
E32k – Enable 32.768kHz Output. This bit when written to a logic 1 enables the 32.768kHz oscillator
frequency to be output on the SQW pin. E32k is set to a 1 when V
CS – Crystal Select. When CS is set to a 0, the oscillator is configured for operation with a crystal that
has a 6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is
disabled in the DS17887 module and should be set to CS = 0.
RCE – RAM Clear Enable. When set to a 1, this bit enables a low level on
of user RAM. When RCE = 0,
PRS – PAB Reset Select. When set to a 0, the
fail. When set to a 1, the
RIE – RAM Clear Interrupt Enable. When RIE is set to a 1, the
clear function is completed.
WIE – Wake-up Alarm Interrupt Enable. When V
pin is driven active low when a wake-up condition occurs, causing the WF bit to be set to 1. When V
then applied, the
affect on the
KSE – Kickstart Interrupt Enable. When V
driven active low when a kickstart condition occurs (
When V
applied, both
the KF bit has no affect on the
PWR
MSB
BIT 7
ABE
are driven low in response to WF being set to 1. When WIE is cleared to a 0, the WF bit has no
CC
is then applied, the
PWR
IRQ
BIT 6
E32k
IRQ
and
or
IRQ
pin is also driven low. If WIE is set while system power is applied, both
PWR
PWR
pins.
are driven low in response to KF being set to 1. When KSE is cleared to a 0,
BIT 5
pin remains active upon entering power fail.
CS
PWR
RCLR
IRQ
or
and the RAM clear function are disabled.
pin is also driven low. If KSE is set to 1 while system power is
IRQ
BIT 4
RCE
pins.
CC
PWR
voltage is absent and KSE is set to a 1, the
22 of 38
pin is set high-z when the DS17885 goes into power
CC
KS
BIT 3
voltage is absent and WIE is set to a 1, the
PRS
pulsed low), causing the KF bit to be set to 1.
CC
is powered up.
IRQ
BIT 2
RIE
pin is driven low when a RAM
RCLR
BIT 1
BAUX
WIE
to clear all 114 bytes
pin for extended
PWR
LSB
BIT 0
IRQ
KSE
pin is
PWR
CC
and
is