DS2722-F-03 MICRO-LINEAR [Micro Linear Corporation], DS2722-F-03 Datasheet - Page 17

• Manufacturer Part Number: DS2722-F-03
• Description: 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
• Manufacturer: MICRO-LINEAR [Micro Linear Corporation]

Prior to transmitting the PLL must tune to the intended RF center frequency of the transmission. This occurs in TXCAL
mode. The Transmit modulation is disabled and any input on the DIN (pin 30) is ignored. The transmit output buffer is
enabled during TXCAL mode. To prevent spurious emissions due to the PLL locking, any external antenna switch or PA
should be disabled during TXCAL mode. For optimum performance we recommend that the second harmonic level
reflected back into the output TRFO (pin 23), be less than –30dBm.
Phase Locked Loop (PLL) and Channel Selection
The PLL synthesizes channel frequencies to a 512kHz resolution, which is more finely spaced than the 1.536MHz
signal bandwidth. Non-overlapping channels are spaced by 2.048MHz where the IF filter and image reject mixer give a
typical adjacent channel rejection of 25dB. There are twelve non-overlapping channels in the 902 to 928MHz ISM band
(see Table 2).
The LO PLL is programmed via a 3-wire serial control bus. Program words are clocked in on the DATA line (pin 5) by
the CLK (pin 6), and loaded into the dividers or control circuits when EN (pin 4) is asserted. There is no check for errors
in the program words. Once loaded, register contents are preserved while VDD is present. The register status and
operation is independent of the mode of operation of the PLL.
The reference signal from an external crystal oscillator at either 6.144MHz or 12.288MHz is fed to a programmable
reference divider. The 1.024MHz reference divider output is fed to the LO phase frequency detector. The PLL prescaler
input comes from the VCO at 1.83GHz, so the 1.024MHz comparison frequency gives 512KHz frequency resolution at
902 to 928MHz.
STANDBY MODE
In STANDBY the ML2722 transceiver is powered down. The only active circuits are the control interfaces, which are
static CMOS to minimize power consumption. The serial control interface (and control registers) remain powered up
and will accept and retain programming data as long as the digital supply is present. The ML2722 serial control
registers should be loaded with control and configuration data before any active mode is selected. The filter alignment
registers are reset at power up.
TEST MODE
The RF to digital functionality of the ML2722 requires special test mode circuitry for IC production test and radio
debugging. A test register, available via the 3-wire serial interface, controls the test multiplexers.
DS2722-F-05
Table 2. Non-Overlapping Channel Frequencies
FINAL DATASHEET
CHANNEL
10
11
12
1
2
3
4
5
6
7
8
9
FREQUENCY IN MHz
903.680
905.728
907.776
909.824
911.872
913.920
915.968
918.016
920.064
922.112
924.160
926.208
DECEMBER 2003
ML2722
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