DS2722-F-03 MICRO-LINEAR [Micro Linear Corporation], DS2722-F-03 Datasheet - Page 24

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DS2722-F-03

Manufacturer Part Number
DS2722-F-03
Description
900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
Manufacturer
MICRO-LINEAR [Micro Linear Corporation]
Datasheet
Transmit Closed Loop Bit (TXCL): DB4
Used to produce a continuous CW transmitter output for product test with RXON low (see Table 11).
Transmit Power Control Bit (TPC): DB5
Controls the state of the TPC/TPQ open-drain output (pin 7). Although this bit may be set at any time, the TPC/TPQ pin
only changes state at the falling edge of RXON (see Table 12).
REGISTER #1, CHANNEL FREQUENCY REGISTER
Channel Frequency Selection Bits (CHQ): <DB11:DB0>
These bits set the channel frequency for the transceiver (see Table 13). With a 6.144MHz or 12.288MHz input to the
REF pin (pin 9), the channel frequency value is calculated by multiplying the CHQ value by 0.512. A 1.024MHz offset is
automatically added in the RECEIVE mode to accommodate the IF frequency. The recommended operating range
value of the CHQ is from 1,024 (400 hex) to 4093 (FFD hex). These bits should be programmed to a valid channel
frequency before XCEN is asserted. The divide ratio is calculated as f
MHz.
DS2722-F-05
FINAL DATASHEET
Table 11. PLL Mode in Transmit Operation
B15
TXCL
0
0
1
TPC
B14
0
1
Table 12. TPC Pin State
0
Table 13. Main Divider
PLL Closed Loop, CW Output
PLL Open Loop, FSK Output
TRANSMIT PLL MODE
PLL divide ratio
TPC PIN STATE
Pulled to Ground
High Impedance
B13 TO B2
B1
0
DECEMBER 2003
C
/0.512, where f
B0
1
C
is the channel frequency in
ML2722
24

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