ex256-ptqg100i Actel Corporation, ex256-ptqg100i Datasheet - Page 6

• Manufacturer Part Number: ex256-ptqg100i
• Description: Fpga Ex Family 4k Gates 256 Cells 250mhz 0.22um Cmos Technology 2.5v 100-pin Tqfp
• Manufacturer: Actel Corporation

Module Organization
C-cell and R-cell logic modules are arranged into
horizontal banks called Clusters, each of which contains
two C-cells and one R-cell in a C-R-C configuration.
Clusters are further organized into modules called
SuperClusters for improved design efficiency and device
performance, as shown in
SuperCluster is a two-wide grouping of Clusters.
Routing Resources
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters
routing architecture also dramatically reduces the
number of antifuses required to complete a circuit,
ensuring the highest possible performance.
Figure 1-2 • C-Cell
1 -2
eX Automotive Family FPGAs
(Figure 1-4 on page
Figure 1-3 on page
DB
D3
D0
D1
D2
1-3. Each
1-3). This
v3.2
A0 B0
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring R-cell
in a given SuperCluster. DirectConnect uses a hardwired
signal path requiring no programmable interconnection to
achieve its fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect
propagation of 0.6 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources, known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
fully automatic place-and-route software to minimize
signal propagation delays.
Sa
A1 B1
path,
Sb
delivering
Y
maximum
pin-to-pin