UPD77110GC NEC [NEC], UPD77110GC Datasheet - Page 58

• Manufacturer Part Number: UPD77110GC
• Description: 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
• Manufacturer: NEC [NEC]

Reset, Interrupt
Timing requirements
Reset timing
WAKEUP timing
Interrupt timing
58
INT1 - INT4
WAKEUP
RESET low-level width
RESET recovery time
WAKEUP low-level width
INT1 - INT4 low-level width
INT1 - INT4 recovery time
PD77111, 77112
RESET
Notes 1. The value on power application is the time from when the supply voltages have reached IV
Parameter
2. Note that t
3. If the low-level width of RESET is greater than 1024t
4. When the power is turned on, a recovery period of 4t
and EV
is no need to use the PLL initialization mode, set the width to less than 1024t
DD
= 2.7 V. A stable clock input is also required.
cC
is I (I = integer of 1 to 16) times that during normal operation in the HALT mode.
t
w(RL)
t
w (WAKEUPL)
Symbol
t
t
t
rec (INT)
t
w (INTL)
rec (R)
w (RL)
t
w (WAKEUPL)
t
w(INTL)
On power application
in STOP mode
During normal operation,
in HALT mode
On power application
Data Sheet U12801EJ4V0DS00
Condition
t
Note 1
Note 4
rec(R)
,
cC
cCX
, the PLL initialization mode is triggered. If there
is necessary before inputting RESET.
2048t
4t
4t
3t
100 +
MIN.
4t
100
3t
cC
cC
cC
cCX
Note 2
Note 2
Note 2
cC
cCX
PD77110, 77111, 77112
TYP.
cC
.
t
rec(INT)
Note 3
MAX.
DD
= 1.8 V
Unit
ns
ns
ns
ns
ns
s
s