PLL202-11D PhaseLink (PLL), PLL202-11D Datasheet - Page 7

• Manufacturer Part Number: PLL202-11D
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Wdt, SST
• Manufacturer: PhaseLink (PLL)

8. BYTE 7: Linear Programming Register (1=Enable, 0=Disable)
Note: This register will be initialized to 0 following WATCHDOG RESET.
9. BYTE 8: WATCHDOG TIMER / Device ID Register (1=Enable, 0=Disable)
Note: *: Default value at power-up
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Motherboard Clock Generator for 440BX Type with 133MHz FSB
Pin#
Pin#
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Default
Default
0*
0*
0*
0*
0*
0*
0*
0*
0
0
0
0
0
0
0
1
Linear programming sign bit ( 0 is “ ”, 1 is “ ” )
Linear programming magnitude bit 6 (MSB)
Linear programming magnitude bit 5
Linear programming magnitude bit 4
Linear programming magnitude bit 3
Linear programming magnitude bit 2
Linear programming magnitude bit 1
Linear programming magnitude bit 0 (LSB)
Watchdog Timer Enable Bit. 1=Enable, 0=Disable
Device ID Bit 6*
Watchdog Time Interval Bit 5 (MSB)
Watchdog Time Interval Bit 4
Watchdog Time Interval Bit 3
Watchdog Time Interval Bit 2
Watchdog Time Interval Bit 1
Watchdog Time Interval Bit 0 (LSB)
PLL202-11 rev. D
Description
Description
Rev D 10/19/00 Page 7
Device ID Bit 5*
Device ID Bit 4*
Device ID Bit 3*
Device ID Bit 2*
Device ID Bit 1*
Device ID Bit 0*