PLL602-03 PhaseLink (PLL), PLL602-03 Datasheet
PLL602-03
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PLL602-03 Summary of contents
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... Low jitter (RMS): 7-9ps period jitter (1 sigma). 3.3V operation. Available in 8-Pin TSSOP or SOIC. DESCRIPTIONS The PLL602- low cost, high performance and low phase noise XO, providing less than -130dBc at 10kHz offset in the 48MHz to 100MHz operating range. The very low jitter ( RMS period jitter) makes this chip ideal for applications requiring reference frequency sources ...
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... Output enable input pin. Disables (tri-state) output when low. Internal pull enables output by default if pin is not connected to low. I Crystal input pin. I Crystal output pin. - Not connected. P Ground pin. SYMBOL CONDITIONS 0.8V to 2.0V with 10pF load 2.0V to 0.8V with 10pF load At VDD/2 PLL602-03 Description MIN. MAX 0 0 0 ...
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... At TTL level (High drive) At TTL level (Low drive) Human Body Model, all pads except XT and XTB Human Body Model, XT and XTB pads SYMBOL MIN. TYP XIN C (xtal PLL602-03 MIN. TYP. MAX. 9 -80 -110 -130 -125 -130 MIN. TYP. MAX. 10 3.13 3.47 2.4 ...
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... Low Phase Noise CMOS XO (48MHz to 100MHz) TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 2.90 3.10 4.30 4.50 6.20 6.60 0.45 0.75 A1 0.65 BSC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL602- PLL602- TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP, D=DIE Rev 12/04/01 Page 4 ...