PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet
PLL202-151
Related parts for PLL202-151
PLL202-151 Summary of contents
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... AGP0_ZCLK/SEL_VIA* PCI0/SEL_SDR_DDR POWER GROUP VDD REF VDD_CPU_CS (2.5V) CPUT (0:1) CPUC (0:1) VDDCPU (3.3V) CPUT (0:1) CPUC (0:1) VDD_APIC (2.5V) APIC (0:1) VDD AGP (0:2) KEY SPECIFICATIONS PCI (1:8) PCI_F VDD 48Mhz 24_48Mhz WDRESET# PLL202-151 PRELIMINARY 1 56 REF0/FS0 VSS 3 54 XIN 4 53 XOUT 5 52 VDDAGP AGP1/SEL_P4_K7 * ...
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... This pin latches the MULTSEL value at power-up. After power-up, this pin acts as PCI2 clock output. MULTSEL is used to selec t the current multiplier for the CPU outputs. This pin has a 20 ohm on-chip series resistor. If MULTSEL=0, IOH=4XIREF. If MULTSEL=1, IOH=6XIREF PLL202-151 PRELIMINARY Description Rev 11/05/01 Page 2 ...
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... VCO divider when SD#= VIA mode, 3.3V CMOS input for SDRAM mode; 2.5V input for DDR mode. In ALI_SIS mode, this input should be connected to ground. O Feedback clock for chipset. Output voltage depends on VDDD. PLL202-151 PRELIMINARY Description Rev 11/05/01 Page 3 ...
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... CPUCS_[T,C] clocks. P 3.3v power supply for CPU[T,C]/CPUOD_[T,C] clocks SEL_SDR_DDR=0 supply DDR at 2.5V, If SELSDR_DDR=1 supply SDRAM at 3.3V P Ground. Reference R (Rr VDD/(3*Rr 221 ; 1% Iref = 5.0mA Rr = 475 ; 1% Iref = 2.32 mA PLL202-151 PRELIMINARY Description Output Current 4*IREF 1. 6*IREF 0. Rev 11/05/01 Page ...
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... N/A 0 111 1 120 0 144 1 156 0 66.6 1 100 0 200 1 133.3 PLL202-151 PRELIMINARY AGP PCI VCO 66.7 33.3 400 66.7 33.3 400 66.7 33.3 400 66.7 33.3 400 66.7 33.3 400 66.7 33.3 800 62.5 31.3 500 83.3 41.7 500 62.5 31.3 500 67.3 33.6 403 420 66.7 33.3 400 66.7 33.3 800 66 ...
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... Byte 1 Address Byte count Data Byte M Address Data Byte M Address Data Data Byte M Byte M+1 P Stop PLL202-151 PRELIMINARY Data Data -------- Byte N Data Data -------- Byte M+N-1 Data Data Byte 2 ...
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... DDRC5/SDRAM11 (1=Active 0=Inactive) PCI_F (1=Active 0=Inactive) DDRT5/SDRAM10 (1=Active 0=Inactive) DDRC4/SDRAM9 (1=Active 0=Inactive) MULTSEL (IREF multiple) MODE Selection. 1= selection through hardware input pin 38 0= selection through I2C control by Byte2.bit[0,7] DDRT4/SDRAM8 (1=Active 0=Inactive) CPUT/CPU0D_T, CPUC/CPU0D_C (1=Active 0=Inactive) CPU_CS_T, CPU_CS_C (1=Active 0=Inactive) PLL202-151 Rev 11/05/01 Page 7 ...
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... Inverted Power-up latched FS3 value (Read only) Inverted Power-up latched FS2 value (Read only) Inverted Power-up latched FS1 value (Read only) Inverted Power-up latched FS0 value (Read only) 48Mhz (1=Active 0=Inactive) 24_48Mhz (1=Active 0=Inactive) PCI5 double drive strength selection. 1=normal, 0=2X REF0 (1=Active 0=Inactive) PLL202-151 Rev 11/05/01 Page 8 ...
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... Linear programming sign bit ( 0 is “ ” “ ” ) Linear programming magnitude bit 6 (MSB) Linear programming magnitude bit 5 Linear programming magnitude bit 4 Linear programming magnitude bit 3 Linear programming magnitude bit 2 Linear programming magnitude bit 1 Linear programming magnitude bit 0 (LSB) PLL202-151 Rev 11/05/01 Page 9 ...
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... Dog falls back to fall back frequency setting in Byte 9. 0 Watchdog Time Interval Bit 5 (MSB) 0 Watchdog Time Interval Bit 4 0 Watchdog Time Interval Bit 3 0 Watchdog Time Interval Bit 2 0 Watchdog Time Interval Bit 1 0 Watchdog Time Interval Bit 0 (LSB) PLL202-151 PRELIMINARY Description Description Description Rev 11/05/01 Page 10 ...
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... Enable VCO-N Counter programming (byte23~24 programming through byte 23~24 0= programming through ROM selection 1 Spread Spectrum mode selection. 1=Center Spread, 0= Down Spread Center Spread: SST<6:0> = Modulation rate * Down Spread: SST<6:0> = Modulation rate * N / PLL202-151 PRELIMINARY Description Description Rev 11/05/01 Page 11 ...
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... AccuSkew Setting II ( 160ps/step) +640ps +480ps Setting applies to the +320ps following outputs: +160ps 1. AGP0_ZCLK Default 2. AGP1, AGP2 -160ps 3. All PCI -320ps -480ps PLL202-151 Skew Setting III (125ps/step) +875ps +750ps +625ps Setting applies to the following outputs: +500ps +375ps 1.DDR/SDRAM (Via mode) +250ps +125ps Default ...
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... Bit <1> 1 160ps per step and Bit <0> 1 Bit <2> 0 These three bits will adjust timing of all PCI signals either Bit <1> 1 positive or negative delay up to +640ps or –480ps with 160ps per step and Bit <0> 1 PLL202-151 Description 5% accuracy. 5% accuracy. 5% accuracy. 5% accuracy. 5% accuracy. 5% accuracy. Rev 11/05/01 Page 13 ...
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... These three bits will program drive strength for DDR[0:2]C, Bit <1> 1 DDR[0:2]T output clocks (see Table 2). Bit <0> 1 Bit <2> 0 These three bits will program drive strength for DDR[3:5]C, Bit <1> 1 DDR[3:5]T output clocks (see Table 2). Bit <0> 1 PLL202-151 Setting III +50% +38% Setting applies to the +25% following outputs +13% 1. PCIF,PCI[0:1] Default 2. PCI[2:5] 3. REF[0:1] -13% -25% ...
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... Table 2). Bit <0> 1 Bit <2> 0 These three bits will program drive strength for REF[0:1] Bit <1> 1 output clocks. (see Table 2). Bit <2> 1 Bit <2> 0 These three bits will program drive strength for FBOUT Bit <1> 1 output clock. (see Table 2). Bit <0> 1 PLL202-151 Description Rev 11/05/01 Page 15 ...
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... These three bits will program all output frequency for Bit <1> 1 DDR/SDRAM clocks (see Table 3). Bit <0> 1 Bit <2> 1 These three bits will program output frequency for Bit <1> 1 AGP0_ZCLK clock (see Table 3). Bit <0> 1 PLL202-151 PRELIMINARY PCI-Divider Default ROM Selection /24 /20 /16 1. PCI /14 /12 /10 /8 Description ...
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... AGP2 clocks (see Table 3). Bit <0> 1 Bit <2> 1 These three bits will program output frequency for all Bit <1> 1 PCI clocks (see Table 3). Bit <0> N<15:0>= VCO*1024/14.31818 <15:0>= VCO*1024/14.31818 PLL202-151 PRELIMINARY Description Description Description Rev 11/05/01 Page 17 ...
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... Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM PROGRAMMING OF CPU FREQUENCY Using Smart- Byte: To simplify traditional loop counter setting, the PLL202-151 device incorporates SMART -BYTE ™ technology with a single byte programming via I2C. Detail of PLL202-151's dual mode frequency programming method is described below: 1. ROM-table Frequency Programming: The pre-defined 32 frequencies found in Frequency table can be accessed through 4 external jumpers ...
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... WDT will generate a 500ms low watchdog reset pulse to provoke a system reset. After system restarts, the PLL202-151 will start from predefined Fall-back Frequency (the value of I2C Byte9, bits(5:3)). If system for any reason fails again at Fall-back Frequency, the internal hardware will then generate a watchdog reset to restart the system from the value of external hardware jumper setting to ensure a safe recovery ...
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... Setting 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 I2C Register Loading: WD-TIMER, WD-ENABLE SUCCESS = Target CPU SUCCESS = Fall-Back CPU System Restart @ PLL202-151 PRELIMINARY START Fall-Back, M, Wait For System Response FAIL - After specified WD -Timer Expired System Restart @ ...
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... DDL pF@66MHz, 2. pF@133MHz, 2.5V 5% DDL crossing of target Freq 3. Logic Inputs IN C XIN & XOUT pins INX PLL202-151 PRELIMINARY MAX 0 0 0 ...
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... PCI, AGP Assumes full supply CPU,PCI_F,PCI, voltage reached within APIC,AGP,REF, 1ms from power-up. Short 48MHz,24MHz cycle exist prior to frequency stabilization. CPU V =3.3V(2.5V PCI,AGP V =3. REF,48MHz,24MHz V =3. PLL202-151 PRELIMINARY = TYP. MAX 175 500 500 250 ...
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... MIN (0.203 - 0.406) 56PIN SSOP 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL202-151 X C PLL202-151 PRELIMINARY 0.025 0.635 0.087 - 0.094 (2.210 - 2.388) 0.095 - 0.110 (2.413 - 2.794) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL ...