PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 9

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

6. BYTE 5: DDR/SDR Clock Register
7. BYTE 6: Vendor ID and Revision ID Register
8. BYTE 7: Linear Programming Register (1=Enable, 0=Disable)
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
Pin#
Pin#
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
35
36
37
38
41
42
43
44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Default
Default
Default
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Description
DDRC3/SDRAM7 (1=Active 0=Inactive)
DDRT3/SDRAM6 (1=Active 0=Inactive)
DDRC2/SDRAM5 (1=Active 0=Inactive)
DDRT2/SDRAM4 (1=Acti ve 0=Inactive)
DDRC1/SDRAM3 (1=Active 0=Inactive)
DDRT1/SDRAM2 (1=Active 0=Inactive)
DDRC0/SDRAM1 (1=Active 0=Inactive)
DDRT0/SDRAM0 (1=Active 0=Inactive)
Description
Revision ID Bit 3 (read only)
Revision ID Bit 2 (read only)
Revision ID Bit 1 (read only)
Revision ID Bit 0 (read only)
Vendor ID Bit 3 (read only)
Vendor ID Bit 2 (read only)
Vendor ID Bit 1 (read only)
Vendor ID Bit 0 (read only)
Linear programming sign bit ( 0 is “ ”, 1 is “ ” )
Linear programming magnitude bit 6 (MSB)
Linear programming magnitude bit 5
Linear programming magnitude bit 4
Linear programming magnitude bit 3
Linear programming magnitude bit 2
Linear programming magnitude bit 1
Linear programming magnitude bit 0 (LSB)
Description
PRELIMINARY
PLL202-151
Rev 11/05/01 Page 9