PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 15

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

16. Buffer Strength Control Register (continued):
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Byte #
Byte
Byte
Byte
17
18
19
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
PCIF,PCI[0:1]
AGP0_ZCLK
AGP[1:2]
REF[0:1]
PCI[2:5]
Strength
Strength
Strength
Strength
Strength
Strength
Strength
FBOUT
USB
Name
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <2>
Bit <2>
Bit <1>
Bit <0>
D e f
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
These three bits will program drive strength for AGP0_ZCLK
output clock (see Table 2).
These three bits will program drive strength for AGP1 and
AGP2 output clocks (see Table 2).
These three bits will program drive strength for 48Mhz and
24_48Mhz output clocks (see Table 2).
These three bits will program drive strength for PCI_F, PCI0,
PCI1 output clocks. (see Table 2).
These three bits will program drive strength for PCI[2:5]
output clocks. (see Table 2).
These three bits will program drive strength for REF[0:1]
output clocks. (see Table 2).
These three bits will program drive strength for FBOUT
output clock. (see Table 2).
PRELIMINARY
Description
PLL202-151
Rev 11/05/01 Page 15