PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 18

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

PROGRAMMING OF CPU FREQUENCY Using Smart- Byte:
To simplify traditional loop counter setting, the PLL202-151 device incorporates SMART -BYTE ™
technology with a single byte programming via I2C. Detail of PLL202-151's dual mode frequency
programming method is described below:
1. ROM-table Frequency Programming:
2. Micro-step Linear Frequency Programming:
FREQUENCY PROGRAMMING EXAMPLE:
1. Procedures to program target CPU frequency to 110 Mhz:
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
The pre-defined 32 frequencies found in Frequency table can be accessed through 4 external
jumpers.
CPU Frequency can be programmed via I2C in fine and linear positive or negative stepping around
selected CPU frequency in Frequency table. The highest step is either +127 or -127. Other bus
frequencies will be changed proportionally with the rate that CPU frequency changes. The formula is
as follow:
A. Locate the closest CPU frequency from Frequency-ROM table: 100 (‘0001)
B. VCO=400, CPU=100, CPUDivider=400/100=4,
C. Solve M (Linear Magnitude factor) in integer:
D. Program I2C register:
F
F
Sign M 6 M 5 M 4 M 3 M 2 M 1 M 0
7
0 0 1 0 1 1 0 0
C P U
P C I
M = (F
6
= 100 + (0.225) * 44 = 109.9 (% of frequency increased vs. ROM Table = 9.9 % )
= 33.3 * (1 + 1.83 %) = 36.6
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
= (110 - 100) / 0.225
= 44
5
Where:
CPU
4
- F
3
CPU
1. M is magnitude factor defined in I2C Byte 7.bit (0:6)
2.
3.
-
2
RO M T A B L E
1
(sign bit) of M is defined in I2C Byte7.bit 7
is a constant equal to 0.9/(CPUDivider) ranging from 0.11~0.45.
F
C P U
0
) /
=
Setting of M = +44 in I2C.BYTE 7
F
C P U . R O M -Table
= (0.9/4)= 0.225
PRELIMINARY
*
M
PLL202-151
Rev 11/05/01 Page 18