PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 16

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

TABLE 3: VCO Divider Programming Summary:
17. VCO Divider Control Register:
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Byte #
Bit<2:0>
Byte
Byte
20
21
111
110
101
100
011
010
001
000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Selection
Default
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
ROM
/8
/7
/6
/5
/4
/3
/2
CPU-Divider
DDR/SDRAM
AGP0_ZCLK
CPU-Host
CPU-CS
Divider
Divider
Divider
Divider
3. DDR/SDRAM
1. CPU-Host
2. CPU-CS
Name
-
-
-
-
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Selection
Default
Default
ROM
/12
/10
/8
/7
/6
/5
/4
AGP-Divider
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1. AGP0_ZCLK
2. AGP[1:2]
Reserved
Reserved
These three bits will program output frequency for
CPU_T and CPU_C clocks (see Table 3).
These three bits will program output frequency for
CPU_CS_C and CPU_CS_T clocks (see Table 3).
Reserved
Reserved
These three bits will program all output frequency for
DDR/SDRAM clocks (see Table 3).
These three bits will program output frequency for
AGP0_ZCLK clock (see Table 3).
PRELIMINARY
Selection
Default
Description
ROM
/24
/20
/16
/14
/12
/10
/8
PCI-Divider
PLL202-151
1. PCI
Rev 11/05/01 Page 16