PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 14

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

TABLE 2: Output Drive Strength Programming Summary:
15. Buffer Strength Control Register:
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Bit<2:0>
Byte #
Bit<0>
Byte
Byte
16
17
111
110
101
100
011
010
001
000
1
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit
Default
Default
+50%
+38%
+25%
+12%
+30%
-12%
-25%
-38%
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
Setting IV
Setting I
1. CPU-Host (K7
CPU Host
Setting applies to the
following outputs
1. CPU-CS
2. DDR[0:2]
3. DDR[3:5]
4. FBOUT
CPU CS
DDR[0:2]
DDR[3:5]
Strength
Strength
Strength
Strength
mode)
Name
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Default
D e f
+40%
+30%
+20%
+10%
-10%
-20%
-30%
0
0
1
1
0
1
1
0
1
1
This bit will allow drive strength to increase 30% for
CPUT/CPUC in K7 mode.
These three bits will program drive strength for CPU_CS_C
and CPU_CS_T output clocks (see Table 2).
These three bits will program drive strength for DDR[0:2]C,
DDR[0:2]T output clocks (see Table 2).
These three bits will program drive strength for DDR[3:5]C,
DDR[3:5]T output clocks (see Table 2).
Setting II
Setting applies to the
following outputs
1. AGP0_ZCLK
2. AGP[1:2]
3. 48M, 24_48MHz
PRELIMINARY
Description
Default
+50%
+38%
+25%
+13%
-13%
-25%
-38%
PLL202-151
Setting III
Setting applies to the
following outputs
1. PCIF,PCI[0:1]
2. PCI[2:5]
3. REF[0:1]
Rev 11/05/01 Page 14