PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 13

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

14. SKEW Control Register (1=Enable, 0=Disable)
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Byte #
Byte
Byte
Byte
Byte
13
14
15
16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
(non-VIA mode)
DDR/SDRAM
DDR/SDRAM
AGP0_ZCLK
(VIA mode)
(VIA mode)
CPU Host
AGP[1:2]
CPU CS
FBOUT
Skew
Skew
Skew
Skew
Skew
Skew
Skew
Skew
PCI
Name
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <3>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
D e f
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
These three bits will adjust timing of CPU_Host signals
(CPUT/CPUC) either positive or negative delay up to +320ps
or –240ps with 80ps per step and
These three bits will adjust timing of CPU_chip_sets signals
(CPU_CS_T/CPU_CS_C) either positive or negative delay up
to +320ps or –240ps with 80ps per step and
These three bits will adjust timing of DDR/SDRAM signals in
non-VIA mode either positive or negative delay up to +320ps
or –240ps with 80ps per step and
These three bits will adjust timing of DDR/SDRAM signals in
VIA buffer mode either positive or negative delay up to
+500ps or –375ps with 125ps per step.
These four bits will adjust timing of FBOUT signal in VIA
buffer mode either positive or negative delay up to +1000ps
or –875ps with 125ps per step.
These three bits will adjust timing of AGP0_ZCLK either
positive or negative delay up to +640ps or –480ps with
These three bits will adjust timing of AGP1 and AGP2 either
positive or negative delay up to +640ps or –480ps with
These three bits will adjust timing of all PCI signals either
positive or negative delay up to +640ps or –480ps with
160ps per step and
160ps per step and
160ps per step and
PRELIMINARY
5% accuracy.
5% accuracy.
5% accuracy.
Description
PLL202-151
5% accuracy.
5% accuracy.
Rev 11/05/01 Page 13
5% accuracy.