PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 11

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

12. BYTE 11: Programming Mode Counter Register (1=Enable, 0=Disable)
13. BYTE 12: Accu-Spread Spectrum Modulation Amplitude Programming Register:
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Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Skew Enable
WDT Status
SST Profile
Accu-SST
NAME
Name
VCO-N
Enable
Enable
SST6
SST5
SST4
SST3
SST2
SST1
SST0
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
-
-
-
Default
Default
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Reserved
Initialization setting for Skew Control and Buffer drive strength registers after
Watch dog reset.
0= Byte 13~19 initialized to 0 after WD-Reset generated.
1= Byte 13~19 unchanged after WD-Reset generated.
Watch Dog Timer Status info (read only)
0= linear, 1= non-linear
Accu-SST programming Enable: 1= via I2C Byte12, 0= via ROM setting
Enable Accu-Skew programming (byte13~15). 1=enable, 0=disable
Enable VCO-N Counter programming (byte23~24)
1= programming through byte 23~24
0= programming through ROM selection
Spread Spectrum mode selection. 1=Center Spread, 0= Down Spread
1.
2.
Center Spread: SST<6:0> = Modulation rate * N /7
Down Spread: SST<6:0> = Modulation rate * N /14
Description
Description
PRELIMINARY
PLL202-151
Rev 11/05/01 Page 11