PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 2

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTIONS
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
XIN
XOUT
REF0/FS0
REF1/Vtt_PWRGD#
DDRT[0:5]/
SDRAM[0,2,4,6,8,10]
DDRC[0:5]/
SD[1,3,5,7,9,11]
AGP1/SEL_K7_P4
PCI1/MULTSEL
Name
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
Number
44,42,38,
43,41,37,
36,32,30
35,31,29
56
12
3
4
1
7
Type
I/O
O
O
O
B
B
B
I
14.318Mhz crystal input to be connected to one end of the crystal
14.318Mhz crystal output
14.318Mhz Reference clock output. This pin latch FS0 value at power-up.
(See Frequency Selection table). It has an internal pull up resistor and 20
ohm on-chip series resistor.
If SEL_K7_P4 = 1 (P4 mode), this 3.3V LVTTL input is a level sensitive
strobe at power up used to determine when FS (0:3) and MULT_SEL1
inputs are valid and all outputs are enable when input is transited to a logic
low. If SEL_K7_P4 = 0 (K7 mode), this input is ignored.
This REF1 has I2C programmable double drive strength and it has a 20
ohm on-chip series resistor.
I n V I A M o d e :
I n A L I _ S I S M o d e :
I n V I A M o d e :
I n A L I _ S I S M o d e :
This pin latches SEL_K7_P4 value at power-up. After power-up, the pin
acts as AGP1 clock output. When SEL_K7_P4=1, it sets to P4 mode.
SEL_K7_P4=0 in K7 mode. This pin has an internal pull-down resistor and a
20 ohm on-chip series resistor.
This pin latches the MULTSEL value at power-up. After power-up, this pin
acts as PCI2 clock output. MULTSEL is used to selec t the current multiplier
for the CPU outputs. This pin has a 20 ohm on-chip series resistor.
If MULTSEL=0, IOH=4XIREF.
If MULTSEL=1, IOH=6XIREF
If SEL_SDR_DDR=0, these outputs provide DDR clock outputs, copies
of BUFIN signals;
If SEL_SDR_DDR=1, these outputs provide SDRAM clock outputs,
copies of BUFIN signals.
If SEL_SDR_DDR=0, these outputs provide DDR clock outputs
generating from internal PLL.
If SEL_SDR_DDR=1, these outputs provide SDRAM clock outputs
generating from internal PLL
If SEL_SDR_DDR=0, these outputs provide DDR clock outputs,
complementary copies of BUFIN signals;
If SEL_SDR_DDR=1, these outputs provide SDRAM clock outputs,
copies of BUFIN signals.
If SEL_SDR_DDR=0, these outputs provide DDR clock outputs
generating from internal PLL.
If SEL_SDR_DDR=1, these outputs provide SDRAM clock outputs
generating from internal PLL
PRELIMINARY
Description
PLL202-151
Rev 11/05/01 Page 2