PLL202-14 PhaseLink (PLL), PLL202-14 Datasheet - Page 6

• Manufacturer Part Number: PLL202-14
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
• Manufacturer: PhaseLink (PLL)

2. BYTE 1: CPU Clock Register (1=Enable, 0=Disable)
3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable)
4. BYTE 3: AGP Clock Register (1=Enable, 0=Disable)
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Pin#
Pin#
35
38
39
42
27
26
23
6
7
9
-
-
-
-
-
-
Default
Default
X
X
X
X
1
1
1
1
1
0
1
1
1
1
1
1
Pin#
20
18
17
16
14
13
11
10
Programmable Clock Generator for VIA Apollo Pro-266
Description
Inverted Power-up latched FS2 value(Read) / WDT Fall-back Frequency selection for FS2
Inverted Power-up latched FS1 value(Read) / WDT Fall-back Frequency selection for FS1
1 = Normal, 0 = PCI Drive Enhanced 25%
Inverted Power-up latched FS0 value(Read) / WDT Fall-back Frequency selection for FS0
CPU2 ( Active/Inactive )
CPU1 ( Active/Inactive )
CPU0 ( Active/Inactive )
APIC2 (Active/Inactive)
Description
Inverted Power-up latched FS3 value(Read) / WDT Fall-back Frequency selection for FS3
0=24MHz, 1=48MHz
48MHz ( Active/Inactive )
24_48MHz ( Active/Inactive )
PCI_F ( Active/Inactive )
AGP2 ( Active/Inactive )
AGP1 ( Active/Inactive )
AGP0 ( Active/Inactive )
Default
1
1
1
1
1
1
1
1
Description
PCI7 ( Active/Inactive )
PCI6 ( Active/Inactive )
PCI5 ( Active/Inactive )
PCI4 ( Active/Inactive )
PCI3 ( Active/Inactive )
PCI2 ( Active/Inactive )
PCI1 ( Active/Inactive )
PCI0 ( Active/Inactive )
PLL202-14
Rev 3/23/01 Page 6