pll2109x Samsung Semiconductor, Inc., pll2109x Datasheet - Page 8

• Manufacturer Part Number: pll2109x
• Description: Description = PLL2109X 100MHz ~ 500MHz FSPLL ;; Function = FSPLL ;; Configuration = 100~500MHz FSPLL ;; Library Type = STD150 ;; Characteristic = 1.2V/3mA
• Manufacturer: Samsung Semiconductor, Inc.

PLL2109X (PRELIMINARY)
CORE LAYOUT GUIDE
1. The Digital power(AVDD12D, AVSS12D) and the analog power(AVDD12A, AVSS12A) must be dedicated to
2. The FOUT and FILTER pins and routings must be placed far from the internal signals in order to avoid cross-
3. Those blocks consume a large amount of digital switching current must be located away from the PLL core.
LAYOUT DESIGN CONSIDERATIONS
The following design considerations must be applied.
1. Jitter is affected by the power noise, substrate noise, etc. It depends on embedded environment noise level.
2. A CMOS-level input reference clock is recommended for signal compatibility with the PLL circuit. Other
3. The use of two, or more PLLs requires special layout considerations. Please consult it with SEC application
4. The PLL core should be placed as close as possible to the dedicated loop filter and analog power and ground
5. It is not recommended to locate high frequency noise-generating signals and cores near the PLL and its I/O
8
PLL only and separated. Please consult PLL dedicated I/O assign with SEC application engineer.
talk.
levels such as TTL may degrade the tolerances.
engineer for more information.
pads & pins.
cells. For example, data buses, high frequency outputs and high current consuming cells.
100MHZ ~ 500MHZ FSPLL