PLL520-17 PhaseLink (PLL), PLL520-17 Datasheet - Page 2

• Manufacturer Part Number: PLL520-17
• Description: , 65-130MHz In, 65-800MHz Out, CMOS
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTIONS
FREQUENCY SELECTION TABLE
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Pin #4
SEL3
Name
VCON
XOUT
CLKT
CLKC
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
GND
VDD
SEL
XIN
0
1
1
1
OE
Pin #5
SEL2
8,9, 10, 14
Number
4,5,15,16
0
0
1
1
1, 12
11
13
2
3
6
7
Pin #15
SEL1
Type
1
1
1
1
O
O
P
P
I
I
I
I
I
Crystal in connector.
Crystal out connector.
Output enable pin.
Frequency control input (0.3V to 3.0V)
GND.
True output PECL (PLL520-18) or LVDS (PLL520-19)
(N/C for PLL520-17)
Complementary output PECL (PLL520-18) or LVDS (PLL520-19)
(CMOS out for PLL520-17).
Multiplier selector pins. These pins have an internal pull-up that will default
SEL to ‘1’ when not connected to GND.
+3.3V VDD.
Pin #16
SEL0
1
1
0
1
Preliminary
Fin x 8
Fin x 4
Fin x 2
No multiplication
PLL520-17/-18/-19
Selected Multiplier
Description
Universal Low Phase Noise IC’s
Rev 4/09/02 Page 2