PLL520-38 PhaseLink (PLL), PLL520-38 Datasheet

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PLL520-38

Manufacturer Part Number
PLL520-38
Description
, 65-130MHz In, 65-130MHz Out, Pecl
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
PLL520-38/-39 is a VCXO IC specifically designed to
pull frequency fundamental crystals from 65MHz to
130MHz, with selectable PECL or LVDS outputs. Its
design was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
VCON
X+
X-
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 130MHz (no PLL).
Low Injection Power for crystal 50uW.
PECL (PLL520-38) or LVDS output (PLL520-39).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in 16-Pin (TSSOP or SOIC).
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
integrated
Oscillator
Amplifier
varicaps
w/
PLL520-38/-39
OE
Q
Q
PIN CONFIGURATION
OUTPUT ENABLE LOGICAL LEVELS
OE input: Logical states defined by PECL levels for PLL520-38
PLL520-38
PLL520-39
Part #
VCON
XOUT
GND
Logical states defined by CMOS levels for PLL520-39
VDD
Preliminary
N/C
N/C
XIN
OE
1
2
3
4
5
6
7
8
0 (Default)
1 (Default)
PLL520-38/-39
OE
1
0
Universal Low Phase Noise IC’s
16
15
14
13
12
11
10
9
Output enabled
Tri-state
Tri-state
Output enabled
N/C
N/C
GND
CLKC
VDD
CLKT
N/C
N/C
State
Rev 4/09/02 Page 1

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PLL520-38 Summary of contents

Page 1

... PLL520-38/-39 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PIN CONFIGURATION XOUT VCON OUTPUT ENABLE LOGICAL LEVELS Part # PLL520-38 PLL520-39 OE input: Logical states defined by PECL levels for PLL520- PLL520-38/-39 Preliminary Universal Low Phase Noise IC’s VDD 1 ...

Page 2

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Preliminary Type I Crystal in connector. I Crystal out connector. I Output enable pin. I Frequency control input (0.3V to 3.0V) P GND. O True output PECL (PLL520-38) or LVDS (PLL520-39) O Complementary output PECL (PLL520-38) or LVDS (PLL520-39). - Not connected. P +3.3V VDD. PLL520-38/-39 Universal Low Phase Noise IC’s Description Rev 4/09/02 Page 2 ...

Page 3

... CONDITIONS CX+ 65MHz to 130MHz CX- (VDD=3.3V Fund. SYMBOL CONDITIONS T From power valid VCXOSTB XTAL C /C < 300 VCON 3.3V, at room temp. VCON = 0 to 3.3V 0V VCON 3.3V, -3dB PLL520-38/-39 Preliminary Universal Low Phase Noise IC’s MIN. MAX -0 -0 -65 150 ...

Page 4

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 SYMBOL CONDITIONS I PECL/LVDS/CMOS 1.25V (LVDS) @ Vdd – 1.3V (PECL) CONDITIONS 77.76MHz 77.76MHz Integrated 12 kHz to 20 MHz at 77.76MHz @10Hz @100Hz -75 -95 PLL520-38/-39 Preliminary Universal Low Phase Noise IC’s MIN. TYP. MAX. 100/80/40 3.13 3. MIN. TYP. ...

Page 5

... (see figure LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80 DIFF 20 PLL520-38/-39 Preliminary Universal Low Phase Noise IC’s MIN. TYP. MAX. 247 355 454 -50 50 1.4 1.6 0.9 1.1 1.125 1.2 1.375 -5.7 -8 MIN. TYP. MAX. ...

Page 6

... PECL t r @80/20% - PECL t f PECL Output Skew VDD OUT 2.0V 50% OUT PECL Transistion Time Waveform DUTY CYCLE PLL520-38/-39 Preliminary Universal Low Phase Noise IC’s MIN. MAX. V – 1.025 DD V – 1.620 DD MIN. TYP. MAX. 0.6 1.5 0.5 1.5 t SKEW Rev 4/09/02 Page 6 ...

Page 7

... TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 A1 0.65 BSC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL520- PLL520-38/-39 Preliminary Universal Low Phase Noise IC’ TEMPERATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE O=TSSOP S=SOIC Rev 4/09/02 Page 7 A ...

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