bc41b143a07 ETC-unknow, bc41b143a07 Datasheet - Page 81

• Manufacturer Part Number: bc41b143a07
• Description: Single Chip Bluetooth
• Manufacturer: ETC-unknow

9.8
Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:8] and PIO[3:0] are powered from
VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO [2:0] are powered from VDD_MEM.
PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are
configured as inputs with weak pull-downs at reset.
PIO[0] and PIO[1] are normally dedicated to RXEN and TXEN respectively, but they are available for general use.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or
PIO[2] can be configured as a request line for an external clock source. This is useful when the clock to
BlueCore4-ROM is provided from a system application specific integrated circuit (ASIC). Using
PSKEY_CLOCK_REQUEST_ENABLE (0x246), this terminal can be configured to be low when BlueCore4-ROM is
in Deep Sleep and high when a clock is required. The clock must be supplied within 4ms of the rising edge of PIO[6]
or PIO[2] to avoid losing timing accuracy in certain Bluetooth operating modes.
BlueCore4-ROM has three general purpose analogue interface pins, AIO[0], AIO[1] and AIO[2]. These are used to
access internal circuitry and control signals. One pin is allocated to decoupling for the on-chip band gap reference
voltage, the other two may be configured to provide additional functionality.
9.8.1
CSR cannot guarantee that these terminal functions remain the same. Refer to the software release note for the
implementation of these PIO lines, as they are firmware build-specific.
CS-101564-DSP12
Name
SAMPLE_FORMAT
Name
CNT_LIMIT
CNT_RATE
SYNC_LIMIT
I/O Parallel Ports
PIO Defaults
Table 9.12: PSKEY_PCM_LOW_JITTER_CONFIG Description
Table 9.11: PSKEY_PCM_CONFIG32 Description
Bit Position
Bit Position
[28:27]
[23:16]
[31:24]
[12:0]
Production Information
© CSR plc 2003-2007
Description
Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample
with 16 cycle slot duration or 8 (0b11) bit sample with 8 cycle
slot duration.
Description
Sets PCM_CLK counter limit
Sets PCM_CLK count rate
Sets PCM_SYNC division relative to PCM_CLK
Device Terminal Descriptions
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