CY28435OXCT SPECTRALINEAR [SpectraLinear Inc], CY28435OXCT Datasheet - Page 6

• Manufacturer Part Number: CY28435OXCT
• Description: Clock Generator for Intel Grantsdale Chipset
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 20, 2006
Byte 2: Control Register 2 (continued)
Byte 3: Control Register 3
Byte 4: Control Register 4
Byte 5: Control Register 5
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
@Pup
HW
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
SRC[T/C]4_SATA
SRC[T/C][7:1]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DOT96[T/C]
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
CPU[T/C]1
SRC[T/C]
PCIF1
Name
Name
PCIF2
PCIF1
PCIF0
Name
Name
FS_E
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]4_SATA with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED, Set = 0
FS_E Reflects the value of the FS_E pin sampled on power-up. 0 = FS_E
was LOW during VTT_PWRGD# assertion.
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED, Set = 1
RESERVED, Set = 1
RESERVED, Set = 1
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Tri-state when SW
PCI_STP# asserted
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
SRC[T/C][7:1] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
RESERVED, Set = 0
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Description
Description
Description
Description
CY28435
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