mx98743 Macronix International Co., mx98743 Datasheet
mx98743
Related parts for mx98743
mx98743 Summary of contents
Page 1
... VeryLongEvents (32-bit Counter) - DataRateMismatches (32-bit Counter) - Auto Partitions (32-bit Counter) - Isolates (32-bit Counter) - SymbolErrorDuringPacket (32-bit Counter) - LastSourceAddress (32-bit Counter) - SourceAddressChange (32-bit Counter) IEEE 802.3u MAU Management Attributes: - FalseCarriers (32-bit Counter) P/N:PM0413 MX98743 100 Base Fast Ethernet Management Chip 1 INDEX FEM REV.3.4, APR 14, 1997 ...
Page 2
... Counter, same as Collision) All the above values as well as XRC registers and counters can be accessed directly through the CPU interface. The FEM occupies a contiguous 4K-byte memory space with 8-bit, 16-bit, and 32-bit datapath choices which allows system designers the maximum flexibility. MX98743 2 INDEX ...
Page 3
... Figure 3-1. 8-Port Management Hub System Diagram The FEM contains a MAC which is capable of transmitting and receiving management packets that are stored in an external SRAM. The CPU reads and writes packets in SRAM through the FEM. uP 8/16/32 MAC FEM MX98743 MANAGEMENT MII Port XRC MX98741 REPEATER CONTROLLER 3 INDEX MX98743 ...
Page 4
... MSA7 MSA8 135 136 MSA9 137 MSA10 138 VDDP MSA11 139 140 MSA12 141 TXCLK TXEN 142 GNDP 143 NC 144 Figure 4-1. 144 Pin PQFP Package MX98743 4 INDEX MX98743 CPUD5 69 CPUD4 68 VDDP 67 CPUD3 66 CPUD2 65 CPUD1 64 CPUD0 63 GNDP 62 RESET 61 GND 60 ...
Page 5
... Transmit Enable. This output becomes active when the first data packet is 142 TXEN O valid on TXD3-0 and goes low after the last packet is clocked out of TXD[3:0]. Transmit Data MII. TXD3-0 are synchronous to TXCLK's rising edge with 1-4 TXD[3:0] O TXD3 being the Most Significant Bit MX98743 DESCRIPTION 5 INDEX ...
Page 6
... Elastic Buffer Over/Underflow status of the XRC. The serial input 30 JBFLO I, TTL data is stored in Register RS[12:1]=01Ah. Isolation. This pin shows the Isolation status of the XRC. The serial input 28 ISO I, TTL data is stored in Register RS[12:1]=01Ch. Table 5-2. Expansion Port, 8 pins DESCRIPTION DESCRIPTION 6 INDEX MX98743 ...
Page 7
... CPU is writing Register RS[12:1]=016h or 01Eh. Register Latch. REGLCH is an input pin when XRCRW is held high and an 35 REGLCH I/O, TTL output pin when XRCRW is held low. Register Clock . This pin is providing the 12.5MHz frequency whenever the FEM 36 REGCK O is accessing the XRC registers. MX98743 DESCRIPTION 7 INDEX ...
Page 8
... CPUD31-0. DWS[1:0] = '00 '01' or '10 bit, = '11' : FEM Register or CPU Selection. When RS12=0, RS[11:0] represents FEM internal registers select pins. When RS12=1, RS[11:0] represents CPU interface address lines. RS[11:0] is mapped to MA[11:0] for 4Kbytes memory: 0h~7ffh for receive buffer, and 800h~fffh for transmit buffer. 8 INDEX MX98743 8 bit, 32 bit. ...
Page 9
... CLK50M I, TTL timing. Table 5-6. Miscellaneous Pins, 2 pin PIN# NAME I/O Reset. Reset is active low and places all the MX98743 logic in a reset mode. 62 RESET I, TTL Test Pin. This is the internal test pin which is internal pulled low. User can 111 TEST I, TTL either leave it uncommented or tie it to ground for normal operation ...
Page 10
... GND/GNDP 96, 97, 107, 122, 132, 143 5, 18, 19, 33, 45, 57, 68, 80, 81, VDD/VDDP 91, 102, 116, 117, 127,138 PIN# NAME I/O 37, 71, 72, 108, 109, NC 144 Table 5-7. Power/Ground, 30 pins DESCRIPTION Ground. Power. Table 5-7. No Connection, 6 pins DESCRIPTION No Connection. Do not connected to these pins. 10 INDEX MX98743 ...
Page 11
... The first word if the Transmit Page contains the transmit byte count information with byte0--Countbit[7:0] and byte 1[3:0]--Countbit[11:8]. RX Page 0 (2K bytes) RX Page 1 (2K bytes) RX Page 2 (2K bytes) TX Page (2K bytes) Byte0 & Byte1 DESCRIPTION Packet received with no error. CRC error. Multicast/Broadcast or Physical Address. Internal four-byte FIFO overrun. 11 INDEX MX98743 ...
Page 12
... Read the Receive Buffer data. 2. Assign Select Page Number to the next page. 3. Read Receive Buffer data. 4. Assign Select Page Number to the next page. 5. Read Receive Buffer data. 6. Assign the Select Page Number to the next page. 7. Re-initial receive enable procedure. MX98743 12 INDEX ...
Page 13
... Select Page Number RX Page 2 Figure 6-2. Received Packet Enters the Buffer Ring Receive Enable Bit Set RX Page 0 RX Page 1 Select Page Number RX Page 2 Figure 6-3. CPU Removed One Packet from the Buffer Ring MX98743 Current Page Number Current Page Number Current Page Number 13 INDEX ...
Page 14
... Port Link/Partition Change Interrupt Status Register x Port Link/Partition Change Interrupt Mask Register x Data Rate Mismatch/Jabber Interrupt Status Register x Data Rate Mismatch/Jabber Interrupt Mask Register x Isolation/SA Change Interrupt Status Register x Isolation/SA Change Interrupt Mask Register x Sample Period Register x Sample Enable Register 14 INDEX MX98743 R/W R/W R/W R R/W R R/W R R/W R R/W R/W R/W ...
Page 15
... Port 1 802.3 Attributes and RMON MIBs x Port 2 802.3 Attributes and RMON MIBs x Port 3 802.3 Attributes and RMON MIBs x Port 4 802.3 Attributes and RMON MIBs x Port 5 802.3 Attributes and RMON MIBs x Port 6 802.3 Attributes and RMON MIBs x Port 7 802.3 Attributes and RMON MIBs 15 INDEX MX98743 R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W ...
Page 16
... Last Source Address Mid 1E x dot3 Last Source Address dot3 Source Address Change dot3 Source Address Change dot3 False Carriers dot3 False Carriers Hi 23-2F x reserved MX98743 IEEE Attributes 16 INDEX R ...
Page 17
... Rmon Ether Stats Pkts 1024 to 1518 Octets Rmon Ether Stats Pkts 1024 to 1518 Octets Rmon Ether History Drop Events Rmon Ether History Drop Events Rmon Ether History Octets Lo MX98743 IEEE Attributes 17 INDEX R ...
Page 18
... Rmon Ether History Oversized Pkts Rmon Ether History Fragments Rmon Ether History Fragments Rmon Ether History Jabbers Rmon Ether History Jabbers Rmon Ether History Collision Rmon Ether History Collision Hi MX98743 RMON MIB 18 INDEX R ...
Page 19
... Select page number of receive buffer for CPU access. [S1,S0] = 00: Page 0; 4-3 S1-0 Reserved 2-1 1:Transmit enable cleared by packet transmitted to FEM reset. 0 TEN 0:Transmit disable REN Table 7-1. DESCRIPTION 01: Page 1; 1x: Page 2. 19 INDEX MX98743 lsb TEN R/W R/W R/W R/W R/W R/W R/W R/W ...
Page 20
... FIFO overrun 1:Receive Buffer Full 1:Packet aborted due to Receive Buffer full. 2 ABT Current Page Number of Receive Buffer for MAC receiver. 1-0 S1 CRC MB Table 7-2. DESCRIPTION 20 MX98743 lsh ABT ...
Page 21
... TX 1:Packet transmitted clear after reset. 0:No packet transmitted. Management Packet Received 1:Packet received cleared after reset. Reserved 0 Reserved Table 7-3. DESCRIPTION 21 INDEX MX98743 lsb R ...
Page 22
... INT 0:Unmasking INT Management Packet Received Interrupt Mask. 1:Masking INT 0:Unmasking INT 1:Reset FEM. 0:Not Reset FEM '0' after RESET pin is asserted low Table 7-4. DESCRIPTION 22 INDEX MX98743 lsb R/W R/W R/W R/W R/W R/W R R/W R/W R/W ...
Page 23
... Set to '1' if Partition Status changes on Port Set to '1' if Partition Status changes on Port All bits are cleared after read and reset Table 7-5. DESCRIPTION 23 INDEX MX98743 lsb R ...
Page 24
... Partition Status change Interrupt on Port 1. 1:Mask Partition Status change interrupt on Port 0. 0 PM0 0:Unmask Partition Status change Interrupt on Port 0. All bits are cleared after reset LM2 LM1 LM0 PM7 PM6 PM5 Table 7-6. DESCRIPTION 24 MX98743 lsb PM4 PM3 PM2 PM1 PM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W ...
Page 25
... Set to '1' if Jabber occurs on Port Set to '1' if Jabber occurs on Port All bits are cleared after read and reset Table 7-7. DESCRIPTION 25 INDEX MX98743 lsb R ...
Page 26
... Jabber interrupt on Port 1. 1 JM1 0:Unmask Jabber Interrupt on Port 1. 1:Mask Jabber interrupt on Port 0. 0 JM0 0:Unmask Jabber Interrupt on Port 0. All bits are cleared after reset Table 7-8. DESCRIPTION 26 INDEX MX98743 lsb R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ...
Page 27
... Set to '1' if Source occurs on Port Set to '1' if Source occurs on Port All bits are cleared after read and reset Table 7-9. DESCRIPTION 27 INDEX MX98743 lsb R ...
Page 28
... SA Change Interrupt on Port 2. 1:Mask SA Change interrupt on Port 1. 1 SM1 0:Unmask SA Change Interrupt on Port 1. 1:Mask SA Change interrupt on Port 0. 0 SM0 0:Unmask SA Change Interrupt on Port IM2 IM1 IM0 SM7 SM6 SM5 Table 7-10. DESCRIPTION 28 MX98743 lsb SM4 SM3 SM2 SM1 SM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ...
Page 29
... SME After reset, this bit is '0'. 8.13 XRC REGISTERS Refer to MX98741 XRC 100BASE TX/FX repeater specification Section Table 7-9. DESCRIPTION 29 INDEX MX98743 lsb lsb SME R/W R/W ...
Page 30
... RS[11:2] are needed, and in 8-bit mode, RS[11:0] are needed. 32-bit Access 16-bit register access (RS 11='0') D31 32-bit counter access (RS11='1') msb Hi D31 48-bit Last SA access Last SA Mid D31 D31 msb D16 D15 lsb msb D16 D15 Last SA Lo D16 D15 Last SA Hi D16 D15 30 MX98743 lsb D0 Lo lsb INDEX ...
Page 31
... Access 16-bit Register Access MSB D15 32-Bit Register Access MSB D15 MSB D15 Interrupt Register etc MIB MIB INDEX MX98743 LSB D0 LSB D0 LSB D0 ...
Page 32
... Last SA Access Byte 1 LSB D15 SA Mid SA Byte 3 LSB D15 Byte 5 LSB D15 SA Byte 0 MSB I/G U Byte 2 MSB LSB Byte 4 MSB LSB INDEX MX98743 D0 MSB D0 MSB D0 ...
Page 33
... Access 16-bit Register Access MSB RS0='1' D7 32-Bit Register Access MSB RS0='1' D7 MSB RS0='1' D7 Interrupt Register etc. RS0=' MIB Lo RS0=' MIB Hi RS0=' INDEX MX98743 LSB D0 LSB D0 LSB D0 ...
Page 34
... Last SA Access Byte 1, RS0='1' LSB D7 SA Mid SA Byte 3, RS0='1' LSB Byte 5, RS0='1' LSB Byte 0, RS0='0' MSB I/G U Byte 2, RS0='1' MSB LSB D7 SA Byte 4, RS0='1' MSB LSB D7 34 INDEX MX98743 D0 MSB D0 MSB D0 ...
Page 35
... Static IDD Current Note : These two parameters will be measured while DC/AC characterization is proceeding. RATING 4. 5. VCC + 0 VCC + 0.5 V -55C to 150 C 600 mW 2000 V Table 10-1. Supply Current CONDITIONS VIN=Switching COCLK=50 MHz VIN=VCC/GND COCLK=Undriven 35 MX98743 VALUE MIN. MAX. UNIT - mA - TBD (note TBD (note) uA INDEX ...
Page 36
... SYMBOL PARAMETER Voh Maximum High Level Input Voltage Vol Minimum Low Level Input Voltage Vil Minimum Low Level Input Voltage Vih Maximum High Level Input Voltage loz Maximum Tri-State Output Leakage Current MX98743 CONDITIONS MIN. GND=0V - 2.0 VI=VCC/GND -1.0 loh=-2mA 2.4 lol=2mA - VOUT=VCC/GND -10 ...
Page 37
... RXCLK rising to REGCK high T21 PTSCEN setup time T22 PTSCEN hold ttime T31 REGCL low to PTSCEN valid T11 Figure 11-1. Clock CLK50M Timing PARAMETER T11 T21 T22 Input Data T31 Output Data PARAMETER 37 MX98743 MIN. MAX. UNIT MIN. MAX. UNIT ...
Page 38
... RW CS T11 RDY CPUD Figure 11-3. CPU Read Cycle SYMBOL PARAMETER T11 CS active to RDY high T12 CS inactive to RDY tristated T21 CPUD to RDY active setup time T22 CS inactive to CPUD tristated T21 T22 T21 MIN. MAX INDEX MX98743 UNIT ...
Page 39
... RW CS T11 RDY T21 CPUD Figure 11-4. CPU Write Cycle SYMBOL PARAMETER T11 CS active to RDY high T12 CS inactive to RDY tristated T21 CPUD active to CPUD valid T22 CS inactive to CPUD hold time MX98743 T21 T22 MIN. MAX INDEX UNIT ...
Page 40
... MSA[12:0] to MOEX inactive T21 MOEX valid low pulse width T22 MD valid to MOEX asserted setup time T23 MD to MOEX asserted hold time Address T12 T21 T22 Data Figure 11-5. SRAM Buffer Read MIN. 1/2*TCLK-4 3/2*TCLK-6 TCLK INDEX MX98743 T23 MAX. UNIT ...
Page 41
... MSA[12:0] MOEX asserted T12 MSA[12:0] to MOEX inactive T21 MOEX valid low pulse width T22 MD valid to MWEX asserted setup time T23 MWEX asserted to MD tristated Address T12 T21 T22 T23 Data MIN. 1/2*TCLK-4 3/2*TCLK-6 TCLK-2 3/2*TCLK-6 1/2*TCLK-4 41 INDEX MX98743 MAX. UNIT ...
Page 42
... I 0.65 [Typ.] .026 [Typ.] J 1.60 [REF] .063 [REF] K 0.8+/-0.2 .031+/-.008 L 0.15 [Typ.] .006 [Typ.] M 0.10 max. .004 max. N 3.35 max. .132 max. O 0.10 min. .004 min. P 3.68 max. .145 max. Note:Each lead centerline is located within .25mm (.01 inch) of its true position [TP maximum material condition. MX98743 42 INDEX ...
Page 43
... Ridder Park Drive, San Jose, CA95131 U.S.A. TEL:+1-408-453-8088 FAX:+1-408-453-8488 JAPAN OFFICE: NFK Kawasaki Building, 8F, 1-2 Higashida-cho, Kawasaki-ku Kawasaki-shi, Kawasaki-ken 210, Japan TEL:+81-44-246-9100 FAX:+81-44-246-9105 TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 43 INDEX MX98743 ...