CY2DP818-2_08 CYPRESS [Cypress Semiconductor], CY2DP818-2_08 Datasheet - Page 3

• Manufacturer Part Number: CY2DP818-2_08
• Description: 1:8 Clock Fanout Buffer
• Manufacturer: CYPRESS [Cypress Semiconductor]

Power Supply Characteristics
Input Receiver Configuration for Differential or LVTTL/LVCMOS
Function Control of the TTL Input Logic used to Accept or Invert the Input Signal
Document #: 38-07588 Rev. *A
ICCD
IC
IC Core
Parameter
INCONFIG Pin 7
Binary Value
Ground
Ground
V
V
DD
DD
1
0
are Disabled
Dynamic Power Supply Current
Total Power Supply Current
Core Current when Output Loads
Input Condition
LVTTL in LVCMOS
LVDS
LVPECL
Input B (–) Pin 11
Input B (–) Pin 11
Input A (+) Pin 10
Input A (+) Pin 10
Input A (+) Pin 10
Input A (+) Pin 10
Input Receiver Family
Input B (–) Pin 11
Input B (–) Pin 11
Description
Single ended, non inverting, inverting, void of bias resistors
Low voltage differential signaling
Low voltage pseudo (positive) emitter coupled logic
PRELIMINARY
V
Input toggling 50% Duty Cycle, Outputs Open
V
Input toggling 50% Duty Cycle, Outputs 50 ohms,
fL=100 MHz
V
Input toggling 50% Duty Cycle, Outputs Disabled,
not connected to VTT fL = 100 MHz
LVTTL/LVCMOS Input Logic
DD
DD
DD
= Max.
= Max.
= Max.
Input Logic
Input
Input
Input
Input
Test Conditions
Input Receiver Type
Output Logic Q Pins, Q1A or Q1
Invert
Invert
Min Typ Max
True
True
1.5
CY2DP818-2
350
2.0
50
Page 3 of 9
MHz
Unit
mA/
mA
mA
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