ct1775 Aeroflex Circuit Technology, ct1775 Datasheet - Page 10

• Manufacturer Part Number: ct1775
• Description: Universal Macair/1553 Dumb Rtu Hybrid Preliminary Data Sheet
• Manufacturer: Aeroflex Circuit Technology

PIN
SCDCT1775 Rev B
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
#
DEC RST
DSC OUT
SEND DATA
CLOCK IN
S/T SELECT
FAIL-SAFE
RT ENABLE
MODE CODE
LATCH DATA 2
ENCENABLE
BROADCAST
TMADD0*
TMADD2*
TMADD4*
TMADDP
CHAN SELECT
ODD PARITY
D15
NAME
PIN FUNCTION AND LOADING TABLE (con’t)
(µA)
100
I
±1
20
20
20
20
20
20
20
20
20
IH
(mA)
±.001
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-2.0
-0.2
I
IL
(mA)
-0.36
I
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-12
OH
(mA)
I
4.0
10
4.0
4.0
4.0
4.0
4.0
3.6
12
OL
A LOW on this input (1 µsec minimum) resets the
decoderto its initialized state, resets COMM/DATA SYNC
to a LOW, and resets VALID WORD to a HIGH.
LOW to HIGH transitions on this output when TAKE
DATA is LOW causes causes receive cycle data shifting to
occur.
A HIGH on this output indicates that transmit cycle data
shifting is occuring.
12 MHz clock input (20pF load) (see text).
A HIGH on this input enables offline wraparound
selftest.The transceiver is disabled and the encoder output
is connected to the decoder input (see text).
A HIGH on this output indicates that a transmitted message
has exceeded 768 µsec, and that transmission has been
terminated. FAIL-SAFE is reset by either FIT ENABLE or
MRST.
A HIGH on this output indicates receipt of a valid
COMMAND word containing the correct 5 bit terminal
address plus address parity. FAIL-SAFE is reset when FIT
ENABLE goes HIGH.
A LOW on this output indicates the reception of a valid
COMMAND word whose sub-address field contains all
ONES or all ZEROES.
A HIGH on this input causes parallel tri-state I/O data on
D0 through D7 to appear at the output of the first rank
transmit register. A LOW locks out the register inputs.
A LOW on this input causes the transmit cycle to start at
the next HIGH to LOW transition of ESC OUT
A HIGH on this output indicates reception of a valid
COMMAND word whose address field contains all ONES,
if BDCST INH is HIGH.
LSB of 5-bit hard-wired terminal address input.
Part of 5-bit hard-wired terminal address input.
MSB of 5-bit hard-wired terminal address input.
Parity bit of hard-wired terminal address. Hard-wired for
odd parity.
A LOW on this input enables DATA SELECT 1, DATA
SELECT 2, LATCH DATA 1, LATCH DATA 2, and ENC
ENABLE inputs.
A HIGH on this output indicates a valid check for odd
parity of terminal address plus parity bits, if ENA PAR
CHECK is a LOW.
MSB of 16 bit parallel tri-state I/O.
DESCRIPTION