ct1775 Aeroflex Circuit Technology, ct1775 Datasheet - Page 11

• Manufacturer Part Number: ct1775
• Description: Universal Macair/1553 Dumb Rtu Hybrid Preliminary Data Sheet
• Manufacturer: Aeroflex Circuit Technology

PIN
SCDCT1775 Rev B
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
#
D13
D11
D9
D7
D5
D3
D1
LOAD DATA 2
+5V
+12V
RX DATA IN
RX STROBE
TX DATA OUT
CASE
DATA SELECT 2
DATA SELECT 1
ENA PAR CHECK
D14
D12
D10
D8
D6
D4
D2
D0
LOAD DATA 1
GND
NAME
PIN FUNCTION AND LOADING TABLE (con’t)
(µA)
I
20
20
20
20
20
20
20
20
40
20
20
20
20
20
20
20
20
20
20
20
20
IH
(mA)
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.4
-1.6
-0.4
-0.4
-0.4
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.4
I
IL
(mA)
I
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
OH
(mA)
I
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
OL
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
LOW on this input causes the data of the D0 through D7
outputs of the first rank transmit register to be loaded into
the second rank transmit register. A HIGH locks out the
second rank register inputs.
+5V power supply input.
+12Vpower supply input.
Inverted receiver input.
A LOW on this input disables the receiver output.
Transmitter output.
Case connection.
A LOW on this input causes the output of the second rank
receiver register to appear on D0 through D7 of the parallel
tri-state I/O.
A LOW on this input causes the output of the second rank
receiver register to appear on D8 through D15 of the
parallel tri-state I/O.
A LOW on this input enables the function of ODD
PARITY.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
Part of 16 bit parallel tri-state I/O.
LSB of 16 bit parallel tri-state I/O.
A LOW on this input causes the data of the D8 through
D15 outputs of the first rank transmit register to be loaded
into the second rank transmit register. A HIGH locks out
the second rank register inputs.
Power supply and logic retum
DESCRIPTION