STV-DCA/CIF-E01 STMICROELECTRONICS [STMicroelectronics], STV-DCA/CIF-E01 Datasheet - Page 55
STV-DCA/CIF-E01
Manufacturer Part Number
STV-DCA/CIF-E01
Description
DUAL-MODE DIGITAL CAMERA CHIPSET
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.STV-DCACIF-E01.pdf
(63 pages)
- Current page: 55 of 63
- Download datasheet (563Kb)
STV0680B+ VV6410/6411/6500
Digital video interface
D[4]
D[3]
D[2]
D[1]
D[0]
QCK
CLKIN
LST/D[5]
FST/D[6]
D[7]
OEB
Digital control signals
RESETB
SUSPEND
Serial interface
SCL
SDA
System clocks
CLKI/CLKIP
Not connected
NC
Key
A
OA
BI
BI
BI
Name
Analogue Input
Analogue Output
Bidirectional
Bidirectional with internal pull-up
Bidirectional with internal pull-down
36
35
34
33
32
42
40
37
38
41
20
31
31
18
17
39
2, 7, 8, 10,13,
14, 19, 22-28,
48
Pin Number
ODT
ODT
BI
ODT
ODT
ODT
ID
ID
ID
BI
BI
ID
Type
Table 21 : VV6500 pin description
VV6500 pinout information and package dimensions
Tri-stateable 5-wire output data bus.
- D[4] is the most significant bit.
- D[4:0] have programmable drive strengths 2, 4 and 6 mA
Tri-stateable data qualification clock.
LVDS negative Clock input
Tri-stateable Line start output
May be configured as tri-stateable output data bit 5 D[5].
Tri-stateable Frame start signal.
May be configured as tri-stateable output data bit 6 D[6].
Tri-stateable Data wire (ms data bit).
May be configured as tri-stateable output data bit 6 D[6].
Digital output (tri-state) enable.
System Reset. Active Low.
May be configured as System Sync. Active Low.
USB Suspend Mode Control signal. Active High
If this feature is not required then the support circuit must pull the pin to
ground. The combination of an active high signal and pull up pad was
chosen to limit current drawn by the device while in suspend mode.
Serial bus clock (input only).
Serial bus data (bidirectional, open drain).
Schmitt Buffered Clock input or LVDS positive Clock input
Not connected
Version 3.4
D
ID
ID
OD
ODT
Digital Input
Digital input with internal pull-up
Digital input with internal pull-down
Digital Output
Tri-stateable Digital Output
Description
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