v54c316162 ETC-unknow, v54c316162 Datasheet

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... CK Access Time ( Features JEDEC Standard 3.3V Power Supply The V54C316162V is ideally suited for high per- formance graphics peripheral applications Single Pulsed RAS Interface Programmable CAS Latency All Inputs are sampled at the positive going edge of clock Programmable Wrap Sequence: Sequential or ...

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... RAS V54C316162V-01 V54C316162V Rev. 2.9 September 2001 Pin Names CLK CKE RAS I/O 16 I/O 15 CAS V SSQ I I –A CCQ SSQ I/O –I/O 1 ...

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... Block Diagram DQMi CLK CKE CS RAS CAS WE DQMi CLK Address V54C316162V Rev.2.9 September 2001 Write Control MUX Logic Memory Array Memory Array Bank 0 512k x 16 Row Decoder Column Address Counter Row Addresses Column Address Buffer ...

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... VDDQ/VSSQ Data Output Power/Ground NC No Connection V54C316162V Rev.2.9 September 2001 Input Function System clock input. Active on the positive rising edge to sample all inptus Activates the CLK signal when high and deactivates the CLK when low. CKE low initiates the power down mode, suspend mode, or the self ...

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... Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. V54C316162V Rev. 2.9 September 2001 ...

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... Full nnn Cn, Cn+1, Cn+2,..... Page V54C316162V Rev. 2.9 September 2001 Similar to the page mode of conventional DRAM’s, burst read or write accesses on any col- umn address are possible once the RAS cycle latches the sense amplifiers. The maximum t the refresh interval time limits the number of random column accesses ...

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... Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by tak- ing CKE “high”. One clock delay is required for mode entry and exit. V54C316162V Rev. 2.9 September 2001 Auto Precharge Two methods are SDRAMs automatic precharge mode, the ...

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... Note: 1. All voltages are referenced may overshoot 2.0 V for pulse width of < 4ns with 3.3V 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. V54C316162V Rev.2.9 September 2001 +0. 3.3 V 0.3 V CCQ Symbol ...

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... These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value Input signals are changed one time during These parameter are measured with continuous data stream during read access and all DQ toggling. V54C316162V Rev. 2.9 September 2001 = 3.3V 0.3V ...

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... CAS(a) to CAS(b) Command pe- CCD riod 21 t Mode Register Set-up time RCS 22 t Power Down Mode Entry Time SB Refresh Cycle 23 t Refresh Period (4096 cycles) REF V54C316162V Rev.2.9 September 2001 0 Limit Values -5 -55 Min. Max. Min. Max. Min. 5 – 5.5 – ...

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... Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. V54C316162V Rev. 2.9 September 2001 0 ...

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... Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. Burst Termination 8.1 Termination of a Full Page Burst Write Operation 8.2 Termination of a Full Page Burst Write Operation V54C316162V Rev.2.9 September 2001 12 V54C316162V ...

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... Burst Read Operation (Burst Length = 4, CAS latency = CLK READ A COMMAND NOP CAS latency = 2 t I/O’s CK2, CAS latency = 3 t I/O’s CK3, V54C316162V Rev. 2.9 September 2001 Bank Col. Addr. t RCD Write NOP with Auto Precharge ...

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... Read to Write Interval (Burst Length = 4, CAS latency = CLK Minimum delay between the Read and Write Commands = 4 cycles DQM COMMAND NOP READ A I/O’s : “H” or “L” V54C316162V Rev.2.9 September 2001 NOP NOP NOP NOP DOUT A DOUT B DOUT B DOUT B ...

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... Length = 4, CAS latency = CLK DQM NOP READ A COMMAND CAS latency = 2 t I/O’s CK1, CAS latency = 3 t I/O’s CK2, : “H” or “L” V54C316162V Rev. 2.9 September 2001 DQW t DQZ 1 Clk Interval BANK A NOP READ A WRITE A ACTIVATE Must be Hi-Z before the Write Command ...

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... Write Interrupted by a Write (Burst Length = 4, CAS latency = CLK COMMAND NOP WRITE A 1 Clk Interval I/O’s DIN A 0 V54C316162V Rev.2.9 September 2001 NOP NOP NOP NOP don’t care DIN A 1 DIN A 2 DIN A 3 Extra data is ignored after termination of a Burst ...

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... Burst Write with Auto-Precharge Burst Length = 2, CAS latency = CLK BANK A COMMAND NOP ACTIVE CAS latency = 2 I/O’s CAS latency = 3 I/O’s V54C316162V Rev. 2.9 September 2001 READ B NOP NOP NOP don’t care DOUT B 0 DOUT B 1 don’t care don’ ...

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... Burst Read with Auto-Precharge Burst Length = 4, CAS latency = CLK COMMAND READ A NOP CAS latency = 2 t I/O’s CK2, CAS latency = 3 t I/O’s CK3, V54C316162V Rev.2.9 September 2001 NOP NOP NOP NOP DOUT A DOUT A 1 DOUT A 2 DOUT ...

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... CAS latency = 3 t I/O’s CK3, 8.2 Termination of a Full Page Burst Write Operation (CAS latency = CLK COMMAND NOP WRITE A CAS latency = 2,3 DIN A 0 I/O’s V54C316162V Rev. 2.9 September 2001 Burst NOP NOP NOP Stop DOUT A DOUT A DOUT A DOUT ...

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... Plastic TSOP-II (400 mil) 0.031 [0.8] +0.002 0.016 0.008 [0.2] M 44x –0.004 +0.05 0.4 –0 0.825 0.005 [20.95 0.13] 1 Does not include plastic or metal protrusion of 0.010 [0.25] max. per side V54C316162V Rev.2.9 September 2001 0.039 0.002 [1 0.05] 0.004 0.002 0.047 Max [0.1 0.05] [1.2 Max] 0.004 [0. V54C316162V +0.003 0.006 ...

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... If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. V54C316162V UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE ...